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| author | Ben Gass <bgass@us.ibm.com> | 2019-05-29 11:59:49 -0400 |
|---|---|---|
| committer | RAJA DAS <rajadas2@in.ibm.com> | 2019-05-31 04:27:54 -0500 |
| commit | 54b282143d67717e6b2fe7b9d66bcbdfe406f88e (patch) | |
| tree | c9bdb9741bba9d71ad245f3e35c5de227d3cc14d /src/import/chips/p9/procedures/xml | |
| parent | fc26a6bd34b5e2ca791780c6742d64522ef6c3eb (diff) | |
| download | talos-sbe-54b282143d67717e6b2fe7b9d66bcbdfe406f88e.tar.gz talos-sbe-54b282143d67717e6b2fe7b9d66bcbdfe406f88e.zip | |
Set IOO clockgate_disable for Axone HW481539 / HW438727
Axone defect HW481539.
Using attribute for HW438727.
Change-Id: Ifa23b2fc07b3a1b324f9815af26f38cd55d45a1b
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/77984
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/77996
Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/xml')
| -rw-r--r-- | src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml | 14 |
1 files changed, 11 insertions, 3 deletions
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml index f572b2ea..2f420f49 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml @@ -3330,10 +3330,11 @@ <!-- ******************************************************************** --> <attribute> <id>ATTR_CHIP_EC_FEATURE_HW438727</id> - <targetType>TARGET_TYPE_PROC_CHIP,TARGET_TYPE_PROC_CHIP</targetType> + <targetType>TARGET_TYPE_PROC_CHIP,TARGET_TYPE_PROC_CHIP,TARGET_TYPE_PROC_CHIP</targetType> <description> - Anything NDD20+,CDD10+: Disable clockgating to allow correct - errors to be reported in ODL c_err_rpt and other error capture + Anything NDD20+,CDD10+,ADD10+: Disable clockgating to allow correct + errors to be reported in ODL c_err_rpt and other error capture. + Axone see: HW481539 </description> <chipEcFeature> <chip> @@ -3350,6 +3351,13 @@ <test>GREATER_THAN_OR_EQUAL</test> </ec> </chip> + <chip> + <name>ENUM_ATTR_NAME_AXONE</name> + <ec> + <value>0x10</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> </chipEcFeature> </attribute> <!-- ******************************************************************** --> |
