diff options
| author | Tsung Yeung <tyeung@us.ibm.com> | 2019-10-23 10:50:36 -0400 |
|---|---|---|
| committer | RAJA DAS <rajadas2@in.ibm.com> | 2019-11-05 08:01:01 -0600 |
| commit | 435e4111a0f523e4088834e36ad445588e594e5a (patch) | |
| tree | e3d0ca2e85aa6cfa93d13f0cc416798776fc33e9 /src/import/chips/p9/procedures/xml | |
| parent | 2e2e7ec7569757cb133d2d5fb21ccac618d828de (diff) | |
| download | talos-sbe-435e4111a0f523e4088834e36ad445588e594e5a.tar.gz talos-sbe-435e4111a0f523e4088834e36ad445588e594e5a.zip | |
Replaces NVDIMM flush sequence with CCS
The current design relies on the power control logic to put the nvdimm
into STR. There have been several defects opened on the nvdimm failing
to save due to STR not entered but no indication of the function failing
to execute. Therefore, the decision has been made to leverage CCS to issue
STR and assert RESETn. This gives us full control of what goes onto the
bus and not have to worry about STR getting exit due to unwanted mainline
traffic.
The same CCS sequence has already been exercised numerous times on AC
powerloss path.
Change-Id: Idd422beea72ee5902674562f5834c1ac9e79fe00
CQ:SW477735
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/85831
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Dev-Ready: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/85880
Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/xml')
| -rw-r--r-- | src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_lib.xml | 28 |
1 files changed, 2 insertions, 26 deletions
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_lib.xml b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_lib.xml index 5e05a1b1..8f78978b 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_lib.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_lib.xml @@ -489,8 +489,8 @@ </hwpError> <hwpError> - <rc>RC_MSS_SRE_MCA_OUT_OF_RANGE</rc> - <description>Indicates a MCA passed to the NVDIMM sre code is out of range</description> + <rc>RC_MSS_SELECT_PORT_MCA_OUT_OF_RANGE</rc> + <description>Indicates a MCA is out of range</description> <ffdc>PROC_TARGET</ffdc> <ffdc>MCA_POS</ffdc> <callout> @@ -498,28 +498,4 @@ <priority>HIGH</priority> </callout> </hwpError> - - <hwpError> - <rc>RC_MSS_RESETN_MCA_OUT_OF_RANGE</rc> - <description>Indicates a MCA passed to the NVDIMM resetn code is out of range</description> - <ffdc>PROC_TARGET</ffdc> - <ffdc>MCA_POS</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - </hwpError> - - <hwpError> - <rc>RC_MSS_STR_NOT_ENTERED</rc> - <description>Indicates a MCA has not entered STR within the allotted time</description> - <ffdc>PROC_TARGET</ffdc> - <ffdc>MCA_POS</ffdc> - <ffdc>MCA_FARB6Q</ffdc> - <ffdc>STR_STATE</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - </hwpError> </hwpErrors> |
