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author | Amit Tendolkar <amit.tendolkar@in.ibm.com> | 2018-06-11 11:36:54 -0500 |
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committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2018-06-17 08:49:48 -0400 |
commit | 130b50b59ad9d7ed8589ff2ea247484ce5f4a102 (patch) | |
tree | 1308ff64d12d101cf6dcf0c83d91e6f9feec2099 /src/import/chips/p9/procedures/xml/error_info | |
parent | 8de7378aac3a569fa62bf21cfa58570c23b3ae84 (diff) | |
download | talos-sbe-130b50b59ad9d7ed8589ff2ea247484ce5f4a102.tar.gz talos-sbe-130b50b59ad9d7ed8589ff2ea247484ce5f4a102.zip |
Adapt p9_sbe_check_master_stop15 for bad path on non-SBE platforms for fleetwood
1. On PENDING/INVALID_STATE RCs, need some FFDC and service actions on FSP
using regular FAPI mechanisms like FAPI_ASSERT and register ffdc colletion
2. SBE still uses existing mechanism and restrictions - optimized for space
a. no fapi error xml based callbacks
b. no fapi error xml based register ffdc collection
c. max local ffdc members < 20
d. depends on p9_collect_deadman_ffdc for FFDC with RC TIMEOUT
3. Compile out extra code on SBE builds
Change-Id: Id35f9a7dbfc7e423bd7cf0846f493a8270a48cd6
CQ: SW430391
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60320
Reviewed-by: RANGANATHPRASAD BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60391
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/xml/error_info')
-rw-r--r-- | src/import/chips/p9/procedures/xml/error_info/p9_sbe_check_master_stop15_errors.xml | 76 |
1 files changed, 71 insertions, 5 deletions
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_check_master_stop15_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_check_master_stop15_errors.xml index 54043657..15b26599 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_check_master_stop15_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_check_master_stop15_errors.xml @@ -5,7 +5,7 @@ <!-- --> <!-- OpenPOWER sbe Project --> <!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2016,2017 --> +<!-- Contributors Listed Below - COPYRIGHT 2016,2018 --> <!-- [+] International Business Machines Corp. --> <!-- --> <!-- --> @@ -30,11 +30,43 @@ Procedure: p9_sbe_check_master_stop15 Indicates the targeted core is either running (hasn't started to enter a STOP state) or is in transition. This return code would be used by the - caller (SBE control loop) to determine whether to continue polling for a - completed transition. - - Note: STOP 11 and STOP 15 are equivalent for POWER9. + caller (FSP/SBE control loop) to determine whether to continue polling + for a completed transition. </description> + + <collectFfdc>p9_eq_clear_atomic_lock,EQ</collectFfdc> + + <collectRegisterFfdc> + <id>CHECK_MASTER_STOP15_FFDC_REGS_PU</id> + <target>PU</target> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CHECK_MASTER_STOP15_FFDC_REGS_EQ</id> + <target>EQ</target> + <targetType>TARGET_TYPE_EQ</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CHECK_MASTER_STOP15_FFDC_REGS_EX</id> + <target>EX</target> + <targetType>TARGET_TYPE_EX</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CHECK_MASTER_STOP15_FFDC_REGS_EC</id> + <target>EC</target> + <targetType>TARGET_TYPE_CORE</targetType> + </collectRegisterFfdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + <callout> + <procedure>LVL_SUPPORT</procedure> + <priority>LOW</priority> + </callout> + <deconfigure> + <target>EC</target> + </deconfigure> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -44,6 +76,40 @@ Indicates the targeted core is no longer pending entering a STOP state but the achieved level is not appropriate. </description> + + <collectFfdc>p9_eq_clear_atomic_lock,EQ</collectFfdc> + + <collectRegisterFfdc> + <id>CHECK_MASTER_STOP15_FFDC_REGS_PU</id> + <target>PU</target> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CHECK_MASTER_STOP15_FFDC_REGS_EQ</id> + <target>EQ</target> + <targetType>TARGET_TYPE_EQ</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CHECK_MASTER_STOP15_FFDC_REGS_EX</id> + <target>EX</target> + <targetType>TARGET_TYPE_EX</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CHECK_MASTER_STOP15_FFDC_REGS_EC</id> + <target>EC</target> + <targetType>TARGET_TYPE_CORE</targetType> + </collectRegisterFfdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + <callout> + <procedure>LVL_SUPPORT</procedure> + <priority>LOW</priority> + </callout> + <deconfigure> + <target>EC</target> + </deconfigure> </hwpError> <!-- ******************************************************************** --> <hwpError> |