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| author | Jacob Harvey <jlharvey@us.ibm.com> | 2016-12-12 14:33:41 -0600 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2018-12-17 21:09:16 -0600 |
| commit | 00d7f23538f6c335253fff4043b76a1f682c536d (patch) | |
| tree | 50d04efcde45726358b1a2dc32043a6828196ab0 /src/import/chips/p9/procedures/xml/attribute_info | |
| parent | 9f22ccd6654f9fe251143ec4779c129c924469c8 (diff) | |
| download | talos-sbe-00d7f23538f6c335253fff4043b76a1f682c536d.tar.gz talos-sbe-00d7f23538f6c335253fff4043b76a1f682c536d.zip | |
Move MRS attributes to eff_config to calc LRDIMMs
Change-Id: Ie2b6d187d67f8bc7ed975e7627fd31ff343e8969
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33774
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Reviewed-by: Brian R. Silver <bsilver@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/69794
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Tested-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/xml/attribute_info')
| -rw-r--r-- | src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml index 642afa20..b57a0efa 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml @@ -2221,6 +2221,52 @@ </attribute> <attribute> + <id>ATTR_EFF_DRAM_RTT_NOM</id> + <targetType>TARGET_TYPE_MCS</targetType> + <description> + RTT_NOM value read to be programmed into MRS02 + For RDIMMS, this is based off of the VPD + For LRDIMMS, this comes from the SPD + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable /> + <array> 2 2 4</array> + <mssAccessorName>eff_dram_rtt_nom</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_EFF_DRAM_RTT_WR</id> + <targetType>TARGET_TYPE_MCS</targetType> + <description> + RTT_WR value read to be programmed into MRS02 + For RDIMMS, this is based off of the VPD + For LRDIMMS, this comes from the SPD + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable /> + <array> 2 2 4</array> + <mssAccessorName>eff_dram_rtt_wr</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_EFF_DRAM_RTT_PARK</id> + <targetType>TARGET_TYPE_MCS</targetType> + <description> + RTT_PARK value read to be programmed into MRS05 + For RDIMMS, this is based off of the VPD + For LRDIMMS, this comes from the SPD + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable /> + <array> 2 2 4</array> + <mssAccessorName>eff_dram_rtt_park</mssAccessorName> + </attribute> + + + <attribute> <id>ATTR_EFF_DIMM_DDR4_BC00</id> <targetType>TARGET_TYPE_MCS</targetType> <description>F0BCW00 Host Interface DQ RTT_NOM Control</description> |
