diff options
author | Joe McGill <jmcgill@us.ibm.com> | 2017-03-02 14:16:43 -0600 |
---|---|---|
committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2017-03-07 08:37:47 -0500 |
commit | b67458b8c4f546adc7aa41090933a571dfeaa080 (patch) | |
tree | d2b56dbd640f03166fc9a44e071bf1f4da0b285b /src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml | |
parent | 67e2a81104c4aba1451b146da460a27bac427b55 (diff) | |
download | talos-sbe-b67458b8c4f546adc7aa41090933a571dfeaa080.tar.gz talos-sbe-b67458b8c4f546adc7aa41090933a571dfeaa080.zip |
nest_attributes.xml -- add 'effective' FBC group/chip ID attributes
expected programming by FW/Cronus:
foreach drawer
if drawer master chip X has no viable memory &&
chip Y in drawer is found to have memory
- set effective FBC group/chip ID attributes for chip X equal to
absolute FBC group/chip ID attribute values for chip Y
- set effective FBC group/chip ID attributes for chip Y equal to
absolute FBC group/chip ID attribute values for chip X
foreach chip Z (excluding X & Y) in drawer
- set effective FBC group/chip ID attributes for chip Z equal to
absolute FBC group/chip ID attribute values for chip Z
done
else
- set effective FBC group/chip ID attributes for all chips in drawer
to their absolute FBC group/chip ID attribute values
fi
done
Change-Id: I80cfe54343eb4f39a6b7dfb77899091a4653454c
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37423
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37426
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml')
-rw-r--r-- | src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml | 39 |
1 files changed, 38 insertions, 1 deletions
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml index 1910993c..b3c0ba7d 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml @@ -324,7 +324,8 @@ <id>ATTR_PROC_FABRIC_SYSTEM_ID</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description> - Logical fabric system ID associated with this chip.Provided by the MRW. + Logical fabric system ID associated with this chip. + Provided by the MRW. </description> <valueType>uint32</valueType> <platInit/> @@ -335,6 +336,8 @@ <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description> Logical fabric group ID associated with this chip. + Directly drives programming of pervasive group ID registers (PIR). + Compared with ATTR_PROC_EFF_FABRIC_GROUP_ID to configure FBC XOR masking. Provided by the MRW. </description> <valueType>uint8</valueType> @@ -346,10 +349,28 @@ </attribute> <!-- ********************************************************************** --> <attribute> + <id>ATTR_PROC_EFF_FABRIC_GROUP_ID</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Effective fabric group ID associated with this chip. + Directly drives programming of chip memory map layout. + Compared with ATTR_PROC_FABRIC_GROUP_ID to configure FBC XOR masking. + </description> + <valueType>uint8</valueType> + <platInit/> + <!-- TODO: Story 155081 + Not supposed to be writeable, PPE needs to resolve this issue in + p9_sbe_attr_setup.C --> + <writeable/> +</attribute> +<!-- ********************************************************************** --> +<attribute> <id>ATTR_PROC_FABRIC_CHIP_ID</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description> Logical fabric chip ID associated with this chip. + Directly drives programming of pervasive chip ID registers (PIR). + Compared with ATTR_PROC_EFF_FABRIC_CHIP_ID to configure FBC XOR masking. Provided by the MRW. </description> <valueType>uint8</valueType> @@ -361,6 +382,22 @@ </attribute> <!-- ********************************************************************** --> <attribute> + <id>ATTR_PROC_EFF_FABRIC_CHIP_ID</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Effective fabric chip ID associated with this chip. + Directly drives programming of chip memory map layout. + Compared with ATTR_PROC_FABRIC_CHIP_ID to configure FBC XOR masking. + </description> + <valueType>uint8</valueType> + <platInit/> + <!-- TODO: Story 155081 + Not supposed to be writeable, PPE needs to resolve this issue in + p9_sbe_attr_setup.C --> + <writeable/> +</attribute> +<!-- ********************************************************************** --> +<attribute> <id>ATTR_PROC_FABRIC_SYSTEM_MASTER_CHIP</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description> |