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authorPrem Shanker Jha <premjha2@in.ibm.com>2018-12-11 05:37:48 -0600
committerRAJA DAS <rajadas2@in.ibm.com>2019-02-11 22:03:38 -0600
commit47f5faba380312fe6d87ad4acca436686afdb244 (patch)
treeb55cf6a6d8bc8fcef9a979d3cb637d03f1bc76f2 /src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml
parentc508f8e9d96e8994616b882f82f118b8085f2845 (diff)
downloadtalos-sbe-47f5faba380312fe6d87ad4acca436686afdb244.tar.gz
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SMF: Populates unsecure HOMER with SC2 instruction.
On an SMF enabled system, if HV engages self save, core must must transition from HV to UV privilege to accomplish this. So, before attempting self save, core must execute SC2 instruction with HV privilege inorder to be a UV. Commit is a partial implementaiton of this solution. It populates a buffer with SC2 instruction which hostboot will copy to an unsecure memory. - Updated attribute tags for MRW Hiding - Removed writing of ATTR_UNSECURE_HOMER_SIZE in deference to attribute default checking Key_Cronus_Test=PM_REGRESS Change-Id: Idb5e219e2a5f9b2274602aedc420f390f34f2609 RTC: 202400 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/69655 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Dev-Ready: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/69661 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml')
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