support chip swap in memory map via FBC XOR mask programming

p9_sbe_fabricinit.C
p9.fbc.ab_hp.scom.initfile
  set PB_CFG_XLATE_ADDR_TO_ID based on XOR of effective & absolute FBC
  group/chip ID attribute values, prior to island mode FBC init

  cleanup register/field constant todos

p9_fbc_utils.C
  parametrize p9_fbc_utils_get_chip_base_address to support calculation of
  origin address based on:
    - effective FBC group/chip ID attributes (EFF_FBC_GRP_CHIP_IDS)
    - effective FBC drawer origin -- effective FBC group ID + chip ID=0
      (EFF_FBC_GRP_ID_ONLY)
    - absolute FBC group/chip ID attributes (ABS_FBC_GRP_CHIP_IDS)

p9_sbe_mcs_setup.C (MCS BAR for HB dcbz support)
  set p9_fbc_utils_get_chip_base_address call to use EFF_FBC_GRP_ID_ONLY
  configures BAR address based on drawer base + HRMOR

p9_sbe_load_bootloader.C
  set p9_fbc_utils_get_chip_base_address call for bootloader load to use
  EFF_FBC_GRP_ID_ONLY (drawer)

  store XSCOM/LPC BAR into bootloader config data structure in exception vector
  (based on chip offset)

p9_mss_eff_grouping.C (MCS/HTM BARs)
p9_pcie_config.C (PCIE MMIO BARs)
p9_rng_init_phase2.C / p9_hcode_image_build.C (NX RNG BAR)
p9_sbe_scominit.C (XSCOM/LPC BARs)
p9_setup_bars.C (MCD, FSP/PSI/NPU/INT MMIO BARs)
  set p9_fbc_utils_get_chip_base_address call to use EFF_FBC_GRP_CHIP_IDS

p9_setup_sbe_config.C
p9_sbe_attr_setup.C
  transmit ATTR_PROC_EFF_FABRIC_[GROUP/CHIP]_ID via scratch6 mailbox

p9_xip_customize.C
  init ATTR_PROC_EFF_FABRIC_[GROUP_CHIP]_ID to zero in image

Change-Id: I3f30bc81a986872c2e7f47422b96bf7bf7c59b06
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37261
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37776
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>

8 files changed, 167 insertions, 86 deletions

diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.C b/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.C
index 85764e37..025667cf 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.C
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.C
@@ -142,14 +142,15 @@ fapi_try_exit:
 
 fapi2::ReturnCode p9_fbc_utils_get_chip_base_address(
     const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+    const p9_fbc_utils_addr_mode_t i_addr_mode,
     uint64_t& o_base_address_nm0,
     uint64_t& o_base_address_nm1,
     uint64_t& o_base_address_m,
     uint64_t& o_base_address_mmio)
 {
-    uint32_t l_fabric_system_id;
-    uint8_t l_fabric_group_id;
-    uint8_t l_fabric_chip_id;
+    uint32_t l_fabric_system_id = 0;
+    uint8_t l_fabric_group_id = 0;
+    uint8_t l_fabric_chip_id = 0;
     uint8_t l_mirror_policy;
     fapi2::buffer<uint64_t> l_base_address;
     const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM;
@@ -157,19 +158,35 @@ fapi2::ReturnCode p9_fbc_utils_get_chip_base_address(
 
     FAPI_DBG("Start");
 
-    // retreive attributes which statically determine chip's position in memory map
+    // retreive attributes which statically determine chips position in memory map
+    // use effective group/chip ID attributes to program position specific address bits
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_SYSTEM_ID, i_target, l_fabric_system_id),
              "Error from FAPI_ATTR_GET (ATTR_FABRIC_SYSTEM_ID)");
-    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_GROUP_ID, i_target, l_fabric_group_id),
-             "Error from FAPI_ATTR_GET (ATTR_FABRIC_GROUP_ID)");
-    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_CHIP_ID, i_target, l_fabric_chip_id),
-             "Error from FAPI_ATTR_GET (ATTR_FABRIC_CHIP_ID)");
+
+    if (i_addr_mode == ABS_FBC_GRP_CHIP_IDS)
+    {
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_GROUP_ID, i_target, l_fabric_group_id),
+                 "Error from FAPI_ATTR_GET (ATTR_FABRIC_GROUP_ID)");
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_CHIP_ID, i_target, l_fabric_chip_id),
+                 "Error from FAPI_ATTR_GET (ATTR_FABRIC_CHIP_ID)");
+    }
+    else
+    {
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EFF_FABRIC_GROUP_ID, i_target, l_fabric_group_id),
+                 "Error from FAPI_ATTR_GET (ATTR_EFF_FABRIC_GROUP_ID)");
+
+        if (i_addr_mode == EFF_FBC_GRP_CHIP_IDS)
+        {
+            FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EFF_FABRIC_CHIP_ID, i_target, l_fabric_chip_id),
+                     "Error from FAPI_ATTR_GET (ATTR_EFF_FABRIC_CHIP_ID)");
+        }
+    }
 
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MEM_MIRROR_PLACEMENT_POLICY, FAPI_SYSTEM, l_mirror_policy),
              "Error from FAPI_ATTR_GET (ATTR_MEM_MIRROR_PLACEMENT_POLICY)");
 
     // apply system ID
-    // occupies one field for large system map, split into three fields for small system map
+    // occupies one field for large system map (three fields for small system map)
     l_base_address.insertFromRight < FABRIC_ADDR_LS_SYSTEM_ID_START_BIT,
                                    (FABRIC_ADDR_LS_SYSTEM_ID_END_BIT - FABRIC_ADDR_LS_SYSTEM_ID_START_BIT + 1) > (l_fabric_system_id);
 
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H b/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H
index ebf633ed..15a6ff37 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER sbe Project                                                  */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -47,6 +47,17 @@
 #include <fapi2.H>
 
 //------------------------------------------------------------------------------
+// Structure definitions
+//------------------------------------------------------------------------------
+
+enum p9_fbc_utils_addr_mode_t
+{
+    EFF_FBC_GRP_CHIP_IDS,  // effective FBC group/chip ID attributes
+    EFF_FBC_GRP_ID_ONLY,   // effective FBC group ID attribute (chip ID=0)
+    ABS_FBC_GRP_CHIP_IDS   // absolute FBC group/chip ID attributes
+};
+
+//------------------------------------------------------------------------------
 // Constant definitions
 //------------------------------------------------------------------------------
 
@@ -91,6 +102,7 @@ fapi2::ReturnCode p9_fbc_utils_override_fbc_stop(
 /// @brief Return base address origin (non-mirrored/mirrored/MMIO) for this chip
 ///
 /// @param[in] i_target Reference to processor chip target
+/// @param[in] i_addr_mode Specifies mode for chip base/origin address calculations
 /// @param[out] o_base_address_nm0 Non-mirrored base address (range 0) for this chip
 /// @param[out] o_base_address_nm1 Non-mirrored base address (range 1) for this chip
 /// @param[out] o_base_address_m Mirrored base address for this chip
@@ -99,10 +111,10 @@ fapi2::ReturnCode p9_fbc_utils_override_fbc_stop(
 ///
 fapi2::ReturnCode p9_fbc_utils_get_chip_base_address(
     const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+    const p9_fbc_utils_addr_mode_t i_addr_mode,
     uint64_t& o_base_address_nm0,
     uint64_t& o_base_address_nm1,
     uint64_t& o_base_address_m,
     uint64_t& o_base_address_mmio);
 
-
 #endif // _P9_FBC_UTILS_H_
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_fabricinit.C b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_fabricinit.C
index 6a956aef..3cd54b7f 100755
--- a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_fabricinit.C
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_fabricinit.C
@@ -50,46 +50,16 @@
 // Constant definitions
 //------------------------------------------------------------------------------
 
-// FBC SCOM register address definitions
-// TODO: these are currently not present in the generated SCOM adddress header
-//       including locally defined address constants here for testing purposes
-const uint64_t PU_FBC_MODE_REG = 0x05011C0A;
-
 // ADU delay/polling constants
 const uint64_t FABRICINIT_DELAY_HW_NS = 1000; // 1us
 const uint64_t FABRICINIT_DELAY_SIM_CYCLES = 200;
 
 // ADU Command Register field/bit definitions
-const uint32_t ALTD_CMD_START_OP_BIT = 2;
-const uint32_t ALTD_CMD_CLEAR_STATUS_BIT = 3;
-const uint32_t ALTD_CMD_RESET_FSM_BIT = 4;
-const uint32_t ALTD_CMD_ADDRESS_ONLY_BIT = 6;
-const uint32_t ALTD_CMD_LOCK_BIT = 11;
-const uint32_t ALTD_CMD_SCOPE_START_BIT = 16;
-const uint32_t ALTD_CMD_SCOPE_END_BIT = 18;
-const uint32_t ALTD_CMD_DROP_PRIORITY_BIT = 20;
-const uint32_t ALTD_CMD_OVERWRITE_PBINIT_BIT = 22;
-const uint32_t ALTD_CMD_TTYPE_START_BIT = 25;
-const uint32_t ALTD_CMD_TTYPE_END_BIT = 31;
-const uint32_t ALTD_CMD_TSIZE_START_BIT = 32;
-const uint32_t ALTD_CMD_TSIZE_END_BIT = 39;
-
-const uint32_t ALTD_CMD_TTYPE_NUM_BITS = (ALTD_CMD_TTYPE_END_BIT - ALTD_CMD_TTYPE_START_BIT + 1);
-const uint32_t ALTD_CMD_TSIZE_NUM_BITS = (ALTD_CMD_TSIZE_END_BIT - ALTD_CMD_TSIZE_START_BIT + 1);
-const uint32_t ALTD_CMD_SCOPE_NUM_BITS = (ALTD_CMD_SCOPE_END_BIT - ALTD_CMD_SCOPE_START_BIT + 1);
-
 const uint32_t ALTD_CMD_TTYPE_PBOP_EN_ALL = 0x3F;
 const uint32_t ALTD_CMD_TSIZE_PBOP_EN_ALL = 0x0B;
 const uint32_t ALTD_CMD_SCOPE_GROUP = 0x3;
 
 // ADU Status Register field/bit definitions
-const uint32_t ALTD_STATUS_ADDR_DONE_BIT = 2;
-const uint32_t ALTD_STATUS_PBINIT_MISSING_BIT = 18;
-const uint32_t ALTD_STATUS_CRESP_START_BIT = 59;
-const uint32_t ALTD_STATUS_CRESP_END_BIT = 63;
-
-const uint32_t ALTD_STATUS_CRESP_NUM_BITS = (ALTD_STATUS_CRESP_END_BIT - ALTD_STATUS_CRESP_START_BIT + 1);
-
 const uint32_t ALTD_STATUS_CRESP_ACK_DONE = 0x04;
 
 
@@ -109,19 +79,40 @@ p9_sbe_fabricinit(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
     fapi2::buffer<uint64_t> l_hp_mode_data;
     bool l_fbc_is_initialized, l_fbc_is_running;
     fapi2::ATTR_PROC_FABRIC_PUMP_MODE_Type l_pump_mode;
+    fapi2::ATTR_PROC_FABRIC_GROUP_ID_Type l_fbc_group_id_abs;
+    fapi2::ATTR_PROC_EFF_FABRIC_GROUP_ID_Type l_fbc_group_id_eff;
+    fapi2::ATTR_PROC_FABRIC_CHIP_ID_Type l_fbc_chip_id_abs;
+    fapi2::ATTR_PROC_EFF_FABRIC_CHIP_ID_Type l_fbc_chip_id_eff;
+    uint8_t l_fbc_xlate_addr_to_id = 0;
 
     // before fabric is initialized, configure resources which live in hotplug registers
     // but which themselves are not hotpluggable
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_PUMP_MODE, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), l_pump_mode),
              "Error from FAPI_ATTR_GET (ATTR_PROC_FABRIC_PUMP_MODE)");
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_GROUP_ID, i_target, l_fbc_group_id_abs),
+             "Error from FAPI_ATTR_GET (ATTR_PROC_FABRIC_GROUP_ID)");
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EFF_FABRIC_GROUP_ID, i_target, l_fbc_group_id_eff),
+             "Error from FAPI_ATTR_GET (ATTR_PROC_EFF_FABRIC_GROUP_ID)");
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_CHIP_ID, i_target, l_fbc_chip_id_abs),
+             "Error from FAPI_ATTR_GET (ATTR_PROC_FABRIC_CHIP_ID)");
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EFF_FABRIC_CHIP_ID, i_target, l_fbc_chip_id_eff),
+             "Error from FAPI_ATTR_GET (ATTR_PROC_EFF_FABRIC_CHIP_ID)");
+
     FAPI_TRY(fapi2::getScom(i_target, PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR, l_hp_mode_data),
              "Error from getScom (PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR)");
 
-    l_hp_mode_data.clearBit<PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_PHYP_IS_GROUP>()    // PHYP_IS_GROUP
-    .clearBit<PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_ADDR_BAR>()                   // Large System Map
-    .clearBit<PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_DCACHE_CAPP>();               // dsable Dcache CAPP mode
+    // determine HW XOR mask based on fabric ID attributes
+    l_fbc_xlate_addr_to_id =  ((l_fbc_group_id_abs << 3) | l_fbc_chip_id_abs);
+    l_fbc_xlate_addr_to_id ^= ((l_fbc_group_id_eff << 3) | l_fbc_chip_id_eff);
+
+    l_hp_mode_data.insertFromRight<PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_XLATE_ADDR_TO_ID,  // XOR mask
+                                   PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_XLATE_ADDR_TO_ID_LEN>(l_fbc_xlate_addr_to_id);
+
+    l_hp_mode_data.clearBit<PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_PHYP_IS_GROUP>()          // PHYP is group
+    .clearBit<PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_ADDR_BAR>()                         // large system map
+    .clearBit<PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_DCACHE_CAPP>();                     // disable Dcache CAPP mode
 
-    if (l_pump_mode == fapi2::ENUM_ATTR_PROC_FABRIC_PUMP_MODE_CHIP_IS_NODE)
+    if (l_pump_mode == fapi2::ENUM_ATTR_PROC_FABRIC_PUMP_MODE_CHIP_IS_NODE)                   // pump mode
     {
         l_hp_mode_data.clearBit<PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_PUMP>();
     }
@@ -160,27 +151,27 @@ p9_sbe_fabricinit(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
     // write ADU Command Register to attempt lock acquisition
     // hold lock until finished with sequence
     FAPI_DBG("Lock and reset ADU ...");
-    l_cmd_data.setBit<ALTD_CMD_LOCK_BIT>();
+    l_cmd_data.setBit<PU_ALTD_CMD_REG_FBC_LOCKED>();
     FAPI_TRY(fapi2::putScom(i_target, PU_ALTD_CMD_REG, l_cmd_data),
              "Error writing ADU Command Register to acquire lock");
 
     // clear ADU status/reset state machine
-    l_cmd_data.setBit<ALTD_CMD_CLEAR_STATUS_BIT>()
-    .setBit<ALTD_CMD_RESET_FSM_BIT>();
+    l_cmd_data.setBit<PU_ALTD_CMD_REG_FBC_CLEAR_STATUS>()
+    .setBit<PU_ALTD_CMD_REG_FBC_RESET_FSM>();
     FAPI_TRY(fapi2::putScom(i_target, PU_ALTD_CMD_REG, l_cmd_data),
              "Error writing ADU Command Register to clear status and reset state machine");
 
     // launch init command
     FAPI_INF("Launching fabric init command via ADU ...");
-    l_cmd_data.setBit<ALTD_CMD_START_OP_BIT>()
-    .clearBit<ALTD_CMD_CLEAR_STATUS_BIT>()
-    .clearBit<ALTD_CMD_RESET_FSM_BIT>()
-    .setBit<ALTD_CMD_ADDRESS_ONLY_BIT>()
-    .setBit<ALTD_CMD_DROP_PRIORITY_BIT>()
-    .setBit<ALTD_CMD_OVERWRITE_PBINIT_BIT>();
-    l_cmd_data.insertFromRight<ALTD_CMD_SCOPE_START_BIT, ALTD_CMD_SCOPE_NUM_BITS>(ALTD_CMD_SCOPE_GROUP);
-    l_cmd_data.insertFromRight<ALTD_CMD_TTYPE_START_BIT, ALTD_CMD_TTYPE_NUM_BITS>(ALTD_CMD_TTYPE_PBOP_EN_ALL);
-    l_cmd_data.insertFromRight<ALTD_CMD_TSIZE_START_BIT, ALTD_CMD_TSIZE_NUM_BITS>(ALTD_CMD_TSIZE_PBOP_EN_ALL);
+    l_cmd_data.setBit<PU_ALTD_CMD_REG_FBC_START_OP>()
+    .clearBit<PU_ALTD_CMD_REG_FBC_CLEAR_STATUS>()
+    .clearBit<PU_ALTD_CMD_REG_FBC_RESET_FSM>()
+    .setBit<PU_ALTD_CMD_REG_FBC_AXTYPE>()
+    .setBit<PU_ALTD_CMD_REG_FBC_DROP_PRIORITY>()
+    .setBit<PU_ALTD_CMD_REG_FBC_OVERWRITE_PBINIT>();
+    l_cmd_data.insertFromRight<PU_ALTD_CMD_REG_FBC_SCOPE, PU_ALTD_CMD_REG_FBC_SCOPE_LEN>(ALTD_CMD_SCOPE_GROUP);
+    l_cmd_data.insertFromRight<PU_ALTD_CMD_REG_FBC_TTYPE, PU_ALTD_CMD_REG_FBC_TTYPE_LEN>(ALTD_CMD_TTYPE_PBOP_EN_ALL);
+    l_cmd_data.insertFromRight<PU_ALTD_CMD_REG_FBC_TSIZE, PU_ALTD_CMD_REG_FBC_TSIZE_LEN>(ALTD_CMD_TSIZE_PBOP_EN_ALL);
     FAPI_TRY(fapi2::putScom(i_target, PU_ALTD_CMD_REG, l_cmd_data),
              "Error writing ADU Command Register to launch init operation");
 
@@ -193,8 +184,9 @@ p9_sbe_fabricinit(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
     FAPI_TRY(fapi2::getScom(i_target, PU_ALTD_STATUS_REG, l_status_data_act),
              "Error polling ADU Status Register");
 
-    l_status_data_exp.setBit<ALTD_STATUS_ADDR_DONE_BIT>();
-    l_status_data_exp.insertFromRight<ALTD_STATUS_CRESP_START_BIT, ALTD_STATUS_CRESP_NUM_BITS>(ALTD_STATUS_CRESP_ACK_DONE);
+    l_status_data_exp.setBit<PU_ALTD_STATUS_REG_FBC_ADDR_DONE>();
+    l_status_data_exp.insertFromRight<PU_ALTD_STATUS_REG_FBC_CRESP_VALUE, PU_ALTD_STATUS_REG_FBC_CRESP_VALUE_LEN>
+    (ALTD_STATUS_CRESP_ACK_DONE);
 
     FAPI_ASSERT(l_status_data_exp == l_status_data_act,
                 fapi2::P9_SBE_FABRICINIT_FAILED_ERR().set_TARGET(i_target).
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_hb_structures.H b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_hb_structures.H
index 9120e625..b8b426e8 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_hb_structures.H
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_hb_structures.H
@@ -55,18 +55,21 @@ enum SbeBootloaderVersion
     // Keep initial version formatted as it was originally
     INIT = 0x901,
     // Later versions use format [release:2][version:2]
-    SAB_ADDED = 0x00090002
+    SAB_ADDED = 0x00090002,
+    MMIO_BARS_ADDED = 0x00090003,
 };
 
 // Structure starts at the bootloader zero address
 struct BootloaderConfigData_t
 {
-    uint32_t version;  // Some kind of version field so we know if there is new data being added
-    uint8_t sbeBootSide;  // 0=SBE side 0, 1=SBE side 1   [ATTR_SBE_BOOT_SIDE]
-    uint8_t pnorBootSide;  // 0=PNOR side A, 1=PNOR side B  [ATTR_PNOR_BOOT_SIDE]
-    uint16_t pnorSizeMB;  // Size of PNOR in MB  [ATTR_PNOR_SIZE]
-    uint64_t blLoadSize;  // Size of Load (Exception vectors and Bootloader)
-    uint8_t secureAccessBit;
+    uint32_t version;         // bytes  4:7  Version field so we know if there is new data being added
+    uint8_t sbeBootSide;      // byte   8    0=SBE side 0, 1=SBE side 1   [ATTR_SBE_BOOT_SIDE]
+    uint8_t pnorBootSide;     // byte   9    0=PNOR side A, 1=PNOR side B  [ATTR_PNOR_BOOT_SIDE]
+    uint16_t pnorSizeMB;      // bytes 10:11 Size of PNOR in MB  [ATTR_PNOR_SIZE]
+    uint64_t blLoadSize;      // bytes 12:19 Size of Load (Exception vectors and Bootloader)
+    uint8_t secureAccessBit;  // byte  20
+    uint64_t xscomBAR;        // bytes 21:28 XSCOM MMIO BAR
+    uint64_t lpcBAR;          // bytes 29:36 LPC MMIO BAR
 };
 
 #endif
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C
index 713b775e..46641c8e 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C
@@ -57,6 +57,7 @@
 const bool PBA_HWP_WRITE_OP = false;
 const int EXCEPTION_VECTOR_NUM_CACHELINES = 96;
 const uint8_t PERV_TO_CORE_POS_OFFSET = 0x20;
+
 //-----------------------------------------------------------------------------------
 // Function definitions
 //-----------------------------------------------------------------------------------
@@ -76,6 +77,9 @@ fapi2::ReturnCode p9_sbe_load_bootloader(
     const uint32_t C_0_THREAD_INFO_RAM_THREAD_ACTIVE_T0 = 18;
     uint64_t l_bootloader_offset;
     uint64_t l_hostboot_hrmor_offset;
+    uint64_t l_drawer_base_address_nm0, l_drawer_base_address_nm1;
+    uint64_t l_drawer_base_address_m;
+    uint64_t l_drawer_base_address_mmio;
     uint64_t l_chip_base_address_nm0, l_chip_base_address_nm1;
     uint64_t l_chip_base_address_m;
     uint64_t l_chip_base_address_mmio;
@@ -126,26 +130,35 @@ fapi2::ReturnCode p9_sbe_load_bootloader(
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_HOSTBOOT_HRMOR_OFFSET, FAPI_SYSTEM, l_hostboot_hrmor_offset),
              "Error from FAPI_ATTR_GET (ATTR_HOSTBOOT_HRMOR_OFFSET)");
 
-    // target base address = (chip non-mirrored base address) +
+    // target base address = (drawer non-mirrored base address) +
     //                       (hostboot HRMOR offset) +
     //                       (bootloader offset)
     FAPI_TRY(p9_fbc_utils_get_chip_base_address(i_master_chip_target,
+             EFF_FBC_GRP_ID_ONLY,
+             l_drawer_base_address_nm0,
+             l_drawer_base_address_nm1,
+             l_drawer_base_address_m,
+             l_drawer_base_address_mmio),
+             "Error from p9_fbc_utils_get_chip_base_address (drawer)");
+
+    FAPI_TRY(p9_fbc_utils_get_chip_base_address(i_master_chip_target,
+             EFF_FBC_GRP_CHIP_IDS,
              l_chip_base_address_nm0,
              l_chip_base_address_nm1,
              l_chip_base_address_m,
              l_chip_base_address_mmio),
-             "Error from p9_fbc_utils_get_chip_base_address");
+             "Error from p9_fbc_utils_get_chip_base_address (chip)");
 
     // add hostboot HRMOR offset and bootloader offset contributions
-    l_chip_base_address_nm0 += l_hostboot_hrmor_offset;
-    l_chip_base_address_nm0 += l_bootloader_offset;
+    l_drawer_base_address_nm0 += l_hostboot_hrmor_offset;
+    l_drawer_base_address_nm0 += l_bootloader_offset;
 
     // check that base address is cacheline aligned
-    FAPI_ASSERT(!(l_chip_base_address_nm0 % FABRIC_CACHELINE_SIZE),
+    FAPI_ASSERT(!(l_drawer_base_address_nm0 % FABRIC_CACHELINE_SIZE),
                 fapi2::P9_SBE_LOAD_BOOTLOADER_INVALID_TARGET_ADDRESS().
                 set_CHIP_TARGET(i_master_chip_target).
                 set_EX_TARGET(i_master_ex_target).
-                set_TARGET_BASE_ADDRESS(l_chip_base_address_nm0).
+                set_TARGET_BASE_ADDRESS(l_drawer_base_address_nm0).
                 set_HRMOR_OFFSET(l_hostboot_hrmor_offset).
                 set_BOOTLOADER_OFFSET(l_bootloader_offset),
                 "Target base address is not cacheline aligned!");
@@ -155,11 +168,11 @@ fapi2::ReturnCode p9_sbe_load_bootloader(
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SBE_HBBL_EXCEPTION_INSTRUCT, FAPI_SYSTEM, l_exception_instruction),
              "fapiGetAttribute of ATTR_SBE_HBBL_EXCEPTION_INSTRUCT failed!");
 
-    l_target_address = l_chip_base_address_nm0;
+    l_target_address = l_drawer_base_address_nm0;
 
     BootloaderConfigData_t l_bootloader_config_data;
 
-    l_bootloader_config_data.version = SAB_ADDED;
+    l_bootloader_config_data.version = MMIO_BARS_ADDED;
 
     //At address X + 0x8 put whatever is in ATTR_SBE_BOOT_SIDE
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SBE_BOOT_SIDE, FAPI_SYSTEM, l_bootloader_config_data.sbeBootSide),
@@ -196,6 +209,15 @@ fapi2::ReturnCode p9_sbe_load_bootloader(
     l_bootloader_config_data.secureAccessBit = l_dataBuf.getBit<4>() ? 1 : 0;
     l_dataBuf.flush<0>();
 
+    // fill in MMIO BARs
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_XSCOM_BAR_BASE_ADDR_OFFSET, FAPI_SYSTEM, l_bootloader_config_data.xscomBAR),
+             "Error from FAPI_ATTR_GET (ATTR_PROC_XSCOM_BAR_BASE_ADDR_OFFSET)");
+    l_bootloader_config_data.xscomBAR += l_chip_base_address_mmio;
+
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_LPC_BAR_BASE_ADDR_OFFSET, FAPI_SYSTEM, l_bootloader_config_data.lpcBAR),
+             "Error from FAPI_ATTR_GET (ATTR_PROC_LPC_BAR_BASE_ADDR_OFFSET)");
+    l_bootloader_config_data.lpcBAR += l_chip_base_address_mmio;
+
     // move data using PBA setup/access HWPs
     l_myPbaFlag.setFastMode(true);  // FASTMODE
 
@@ -210,7 +232,7 @@ fapi2::ReturnCode p9_sbe_load_bootloader(
         l_myPbaFlag.setOperationType(p9_PBA_oper_flag::DMA); // DMA operation
     }
 
-    while (l_target_address < (l_chip_base_address_nm0 + i_payload_size + l_exception_vector_size))
+    while (l_target_address < (l_drawer_base_address_nm0 + i_payload_size + l_exception_vector_size))
     {
         // invoke PBA setup HWP to prep stream
         FAPI_TRY(p9_pba_setup( i_master_chip_target,
@@ -224,7 +246,7 @@ fapi2::ReturnCode p9_sbe_load_bootloader(
 
         // call PBA access HWP per cacheline to move payload data
         while (l_num_cachelines_to_roll &&
-               (l_target_address < (l_chip_base_address_nm0 + i_payload_size + l_exception_vector_size)))
+               (l_target_address < (l_drawer_base_address_nm0 + i_payload_size + l_exception_vector_size)))
         {
             if ((l_cacheline_num == 0) && (l_exception_instruction != 0))
             {
@@ -232,27 +254,27 @@ fapi2::ReturnCode p9_sbe_load_bootloader(
                 //The rest of the exception vector is what was in SBE_HBBL_EXCEPTION_INSTRUCT replicated multiple times (until the end of 12KB of exception vector data)
                 for (uint32_t i = 0; i < FABRIC_CACHELINE_SIZE; i++)
                 {
-                    //At address X put whatever is in l_branch_to_12
+                    //At address X (0-3) put whatever is in l_branch_to_12
                     if (i < 4)
                     {
                         l_data_to_pass_to_pba_array[i] = (l_branch_to_12 >> (24 - 8 * i )) & 0xFF;
                     }
-                    //At address X + 0x4 put the HBBL_STRUCT_VERSION
+                    //At address X + 0x4 (4-7) put the HBBL_STRUCT_VERSION
                     else if (i < 8)
                     {
                         l_data_to_pass_to_pba_array[i] = (l_bootloader_config_data.version >> (24 - 8 * ((i - 4) % 4))) & 0xFF;
                     }
-                    //At address X + 0x8 put the SBE_BOOT_SIDE
+                    //At address X + 0x8 (8) put the SBE_BOOT_SIDE
                     else if (i == 8)
                     {
                         l_data_to_pass_to_pba_array[i] = l_bootloader_config_data.sbeBootSide;
                     }
-                    //At address X + 0x9 put the PNOR_BOOT_SIDE
+                    //At address X + 0x9 (9) put the PNOR_BOOT_SIDE
                     else if (i  == 9)
                     {
                         l_data_to_pass_to_pba_array[i] = l_bootloader_config_data.pnorBootSide;
                     }
-                    //At address X + 0xA pu the PNOR_SIZE
+                    //At address X + 0xA (10-11) pu the PNOR_SIZE
                     else if (i == 10)
                     {
                         l_data_to_pass_to_pba_array[i] = l_bootloader_config_data.pnorSizeMB >> 8 & 0xFF;
@@ -261,16 +283,26 @@ fapi2::ReturnCode p9_sbe_load_bootloader(
                     {
                         l_data_to_pass_to_pba_array[i] = l_bootloader_config_data.pnorSizeMB & 0xFF;
                     }
-                    //At address X + 0xC put the total load size
+                    //At address X + 0xC (12-19) put the total load size
                     else if (i < 20)
                     {
                         l_data_to_pass_to_pba_array[i] = (l_bootloader_config_data.blLoadSize >> (56 - 8 * ((i - 12) % 8))) & 0xFF;
                     }
-                    //At address X + 0x14 put the secure access bit
+                    //At address X + 0x14 (20) put the secure access bit
                     else if (i == 20)
                     {
                         l_data_to_pass_to_pba_array[i] = l_bootloader_config_data.secureAccessBit;
                     }
+                    //At address X + 0x1B (21-28) put the XSCOM BAR
+                    else if (i < 29)
+                    {
+                        l_data_to_pass_to_pba_array[i] = (l_bootloader_config_data.xscomBAR >> (56 - 8 * ((i - 21) % 8))) & 0xFF;
+                    }
+                    //At address X + 0x1B (29-36) put the LPC BAR
+                    else if (i < 37)
+                    {
+                        l_data_to_pass_to_pba_array[i] = (l_bootloader_config_data.lpcBAR >> (56 - 8 * ((i - 29) % 8))) & 0xFF;
+                    }
                     //Fill the rest with the exception vector instruction
                     else
                     {
@@ -304,7 +336,7 @@ fapi2::ReturnCode p9_sbe_load_bootloader(
                                    l_firstAccess,
                                    (l_num_cachelines_to_roll == 1) ||
                                    ((l_target_address + FABRIC_CACHELINE_SIZE) >=
-                                    (l_chip_base_address_nm0 + i_payload_size + l_exception_vector_size)),
+                                    (l_drawer_base_address_nm0 + i_payload_size + l_exception_vector_size)),
                                    l_data_to_pass_to_pba_array), "Error from p9_pba_access");
             l_firstAccess = false;
             // decrement count of cachelines remaining in current stream
@@ -337,7 +369,7 @@ fapi2::ReturnCode p9_sbe_load_bootloader(
         l_dataBuf.flush<0>().setBit<C_0_THREAD_INFO_RAM_THREAD_ACTIVE_T0>();
         FAPI_TRY(fapi2::putScom(l_coreTarget, C_0_THREAD_INFO, l_dataBuf),
                  "Error setting thread active for t0");
-        l_dataBuf.flush<0>().insertFromRight<0, 64>(l_chip_base_address_nm0);
+        l_dataBuf.flush<0>().insertFromRight<0, 64>(l_drawer_base_address_nm0);
         //call RamCore put_reg method
         FAPI_TRY(ram.put_reg(REG_SPR, 313, &l_dataBuf), "Error ramming HRMOR");
     }
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.C b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.C
index acf90b78..2e743e7a 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.C
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.C
@@ -258,9 +258,10 @@ fapi2::ReturnCode p9_sbe_mcs_setup(const fapi2::Target<fapi2::TARGET_TYPE_PROC_C
 #endif
 
         // determine base address
-        //      = (chip non-mirrored base address) + (hostboot HRMOR offset)
+        //      = (drawer non-mirrored base address) + (hostboot HRMOR offset)
         //      min MCS base size is 4GB, local HB will always be below
         FAPI_TRY(p9_fbc_utils_get_chip_base_address(i_target,
+                 EFF_FBC_GRP_ID_ONLY,
                  l_chip_base_address_nm0,
                  l_chip_base_address_nm1,
                  l_chip_base_address_m,
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C
index 8cb7cbbb..1671e5f5 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C
@@ -154,6 +154,7 @@ p9_sbe_scominit(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
 
     // determine base address of chip nm/m/mmmio regions in real address space
     FAPI_TRY(p9_fbc_utils_get_chip_base_address(i_target,
+             EFF_FBC_GRP_CHIP_IDS,
              l_base_addr_nm0,
              l_base_addr_nm1,
              l_base_addr_m,
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C
index 8ea0bb77..a96f300f 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C
@@ -82,6 +82,10 @@ enum P9_SETUP_SBE_CONFIG_scratch4
     ATTR_SLOW_PCI_REF_CLOCK_BIT        = 5,
 
     // Scratch_reg_6
+    ATTR_PROC_EFF_FABRIC_GROUP_ID_STARTBIT = 17,
+    ATTR_PROC_EFF_FABRIC_GROUP_ID_LENGTH = 3,
+    ATTR_PROC_EFF_FABRIC_CHIP_ID_STARTBIT = 20,
+    ATTR_PROC_EFF_FABRIC_CHIP_ID_LENGTH = 3,
     ATTR_PUMP_CHIP_IS_GROUP            = 23,
     ATTR_PROC_FABRIC_GROUP_ID_STARTBIT = 26,
     ATTR_PROC_FABRIC_GROUP_ID_LENGTH   = 3,
@@ -548,6 +552,14 @@ fapi2::ReturnCode p9_sbe_attr_setup(const
             FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_PROC_FABRIC_CHIP_ID, i_target_chip,
                                    l_read_3));
 
+            l_read_scratch_reg.extractToRight<17, 3>(l_read_2);
+            l_read_scratch_reg.extractToRight<20, 3>(l_read_3);
+
+            FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_PROC_EFF_FABRIC_GROUP_ID, i_target_chip,
+                                   l_read_2));
+            FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_PROC_EFF_FABRIC_CHIP_ID, i_target_chip,
+                                   l_read_3));
+
         }
         else
         {
@@ -589,6 +601,17 @@ fapi2::ReturnCode p9_sbe_attr_setup(const
             l_read_scratch_reg.insertFromRight< ATTR_PROC_FABRIC_GROUP_ID_STARTBIT, ATTR_PROC_FABRIC_GROUP_ID_LENGTH >(l_read_1);
             l_read_scratch_reg.insertFromRight< ATTR_PROC_FABRIC_CHIP_ID_STARTBIT, ATTR_PROC_FABRIC_CHIP_ID_LENGTH >(l_read_2);
 
+            FAPI_DBG("Reading ATTR_PROC_EFF_FABRIC_GROUP and CHIP_ID");
+            FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EFF_FABRIC_GROUP_ID, i_target_chip,
+                                   l_read_1));
+            FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EFF_FABRIC_CHIP_ID, i_target_chip,
+                                   l_read_2));
+
+            l_read_scratch_reg.insertFromRight< ATTR_PROC_EFF_FABRIC_GROUP_ID_STARTBIT, ATTR_PROC_EFF_FABRIC_GROUP_ID_LENGTH >
+            (l_read_1);
+            l_read_scratch_reg.insertFromRight< ATTR_PROC_EFF_FABRIC_CHIP_ID_STARTBIT, ATTR_PROC_EFF_FABRIC_CHIP_ID_LENGTH >
+            (l_read_2);
+
             FAPI_DBG("Setting up value of Scratch_reg6");
             //Setting SCRATCH_REGISTER_6 register value
             FAPI_TRY(fapi2::putScom(i_target_chip, PERV_SCRATCH_REGISTER_6_SCOM,