Pstates/Lab: Add unblocking for DPLL/VRM/VDM/Resclk to pm_suspend

This is a temporary solution to unblock analong controls until the
full pm_suspend is implemented and tested.

Change-Id: Iea751b44b3d7b1e93583481304759d0dff971e83
RTC: 174963
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41171
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43179
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>

1 files changed, 107 insertions, 72 deletions

diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_suspend_powman.C b/src/import/chips/p9/procedures/hwp/pm/p9_suspend_powman.C
index 7cd88bce..244ef6e9 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_suspend_powman.C
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_suspend_powman.C
@@ -64,39 +64,54 @@ extern "C" {
         // mark HWP entry
         FAPI_DBG("Entering ...\n");
 
-        fapi2::buffer<uint64_t> l_pba_data(0);
-        fapi2::buffer<uint64_t> l_occflg_data(0);
-        fapi2::buffer<uint64_t> l_occs2_data(0);
-        fapi2::buffer<uint64_t> l_ocr_reg_data(0);
-        fapi2::buffer<uint64_t> l_ppe_xixcr_data(0);
-        uint64_t l_xixcr_force_halt_cmd = 0b111;
-        bool l_pgpe_in_safe_mode = false;
-
-        // SBE messages request to OCC to enter safe state via OCC_Flag[REQUEST_OCC_SAFE_STATE] , which OCC polls every 500us. This does not cause any errors to be logged.
-        // In response PGPE will detect missing OCC heartbeat after an additional 8ms and go into "safe mode". This is cleanly handled on OCC across all chips.
-        l_occflg_data.setBit<p9hcd::REQUEST_OCC_SAFE_STATE>();
-        FAPI_TRY(fapi2::putScom(i_target, PU_OCB_OCI_OCCFLG_SCOM2, l_occflg_data),
-                 "Error setting OCC Flag register bit REQUEST_OCC_SAFE_STATE");
-
-        // SBE waits for PGPE to set OCC Scratch2[PGPE_SAFE_MODE_ACTIVE]. SBE Timeout after 33ms, then sets OCC Flag[PGPE_SAFE_MODE] to request PGPE into "safe mode" manually. SBE polls on OCC Scratch2[PGPE_SAFE_MODE_ACTIVE] again, timeout after 8ms
-        //TODO put in the delays here for 33ms and 8ms
-        for (uint32_t i = 0; i < c_tries_before_timeout; i++)
+
+
+        // @todo RTC 147282
+        // @todo RTC 168889
+        // Until the PM suspend flow is fully defined and tested, switch the analog control ownership away from
+        // the CME and back to SCOM.
+        // This is sufficient until pstates have been started
+
+        FAPI_INF("Restoring SCOM Control of the IVRM, ACLK, VDATA, and DPLL.");
+        FAPI_INF("NOTE: This is not the full pm_suspend @todo RTC 147282, 168889");
+
+        fapi2::buffer<uint64_t> l_qpmmr_data(0);
+
+        l_qpmmr_data.setBit<EQ_QPPM_QPMMR_CME_INTERPPM_IVRM_ENABLE>();
+        l_qpmmr_data.setBit<EQ_QPPM_QPMMR_CME_INTERPPM_ACLK_ENABLE>();
+        l_qpmmr_data.setBit<EQ_QPPM_QPMMR_CME_INTERPPM_VDATA_ENABLE>();
+        l_qpmmr_data.setBit<EQ_QPPM_QPMMR_CME_INTERPPM_DPLL_ENABLE>();
+
+        auto l_quad_vector = i_target.getChildren<fapi2::TARGET_TYPE_EQ>();
+
+        for (auto quad_it : l_quad_vector)
         {
-            FAPI_TRY(fapi2::getScom(i_target, PU_OCB_OCI_OCCS2_SCOM, l_occs2_data), "Error reading OCC Scratch 2 register");
 
-            if(l_occs2_data.getBit<p9hcd::PGPE_SAFE_MODE_ACTIVE>())
-            {
-                l_pgpe_in_safe_mode = true;
-                break;
-            }
+            FAPI_TRY(fapi2::putScom(quad_it, EQ_QPPM_QPMMR_CLEAR, l_qpmmr_data), "Error writing to QPMMR");
         }
 
-        if (!l_pgpe_in_safe_mode)
-        {
 
-            l_occflg_data.flush<0>().setBit<p9hcd::PGPE_SAFE_MODE>();
-            FAPI_TRY(fapi2::putScom(i_target, PU_OCB_OCI_OCCFLG_SCOM2, l_occflg_data), "Error setting OCC Flag register bit 2");
 
+        // Real code that will be re-enabled with the todos.
+        if (0)
+        {
+
+            fapi2::buffer<uint64_t> l_pba_data(0);
+            fapi2::buffer<uint64_t> l_occflg_data(0);
+            fapi2::buffer<uint64_t> l_occs2_data(0);
+            fapi2::buffer<uint64_t> l_ocr_reg_data(0);
+            fapi2::buffer<uint64_t> l_ppe_xixcr_data(0);
+            uint64_t l_xixcr_force_halt_cmd = 0b111;
+            bool l_pgpe_in_safe_mode = false;
+
+            // SBE messages request to OCC to enter safe state via OCC_Flag[REQUEST_OCC_SAFE_STATE] , which OCC polls every 500us. This does not cause any errors to be logged.
+            // In response PGPE will detect missing OCC heartbeat after an additional 8ms and go into "safe mode". This is cleanly handled on OCC across all chips.
+            l_occflg_data.setBit<p9hcd::REQUEST_OCC_SAFE_STATE>();
+            FAPI_TRY(fapi2::putScom(i_target, PU_OCB_OCI_OCCFLG_SCOM2, l_occflg_data),
+                     "Error setting OCC Flag register bit REQUEST_OCC_SAFE_STATE");
+
+            // SBE waits for PGPE to set OCC Scratch2[PGPE_SAFE_MODE_ACTIVE]. SBE Timeout after 33ms, then sets OCC Flag[PGPE_SAFE_MODE] to request PGPE into "safe mode" manually. SBE polls on OCC Scratch2[PGPE_SAFE_MODE_ACTIVE] again, timeout after 8ms
+            //TODO put in the delays here for 33ms and 8ms
             for (uint32_t i = 0; i < c_tries_before_timeout; i++)
             {
                 FAPI_TRY(fapi2::getScom(i_target, PU_OCB_OCI_OCCS2_SCOM, l_occs2_data), "Error reading OCC Scratch 2 register");
@@ -107,59 +122,79 @@ extern "C" {
                     break;
                 }
             }
-        }
 
-        //TODO @todo RTC 164109 for when this is implemented in PGPE Hcode
-        /*FAPI_ASSERT(l_pgpe_in_safe_mode, fapi2::P9_PGPE_SAFEMODE_TIMEOUT().set_TARGET(i_target).set_OCCFLGREG(l_occflg_data),
-                    "PGPE did not set OCC Flag bit 6");
-        */
-        // In response, PGPE safe mode tell CME to go into safe mode.
-
-        // Suspend PGPE, SGPE, and CME from processing Pstate, WOF, and STOP entry/exit requests.
-        // (see above) Use OCC flag register bit 3 to request PM Complex suspend.:  In response, PGPE will stop processing Pstates, message SGPE to stop calling 24x7 thread andsuspend responding to Stop entry & exit. PGPE will message CME to stop processing Stop states??????.; then wait for ACK from each engine
-        l_occflg_data.flush<0>().setBit<p9hcd::PM_COMPLEX_SUSPEND>();
-        FAPI_TRY(fapi2::putScom(i_target, PU_OCB_OCI_OCCFLG_SCOM2, l_occflg_data), "Error setting OCC Flag register bit 3");
-        // TODO @todo RTC 164110 How to wait for ACK from each engine - an update is needed once the PGPE implements the function
-
-        // SBE would then issue the "halt OCC complex" (2 SCOMs) to stop OCC instructions (The "halt OCC complex" is that when it is removed the OCC complex won't start executing instructions. The prevent execution overrides any incoming start requests until released)
-        l_ocr_reg_data.setBit<PU_OCB_PIB_OCR_OCC_DBG_HALT>();
-        FAPI_TRY(fapi2::putScom(i_target, PU_OCB_PIB_OCR_OR, l_ocr_reg_data), "Error writing to OCR register");
-
-        // SBE then halts GPE0-3.
-        l_ppe_xixcr_data.insertFromRight<PU_GPE0_PPE_XIXCR_XCR, PU_GPE0_PPE_XIXCR_XCR_LEN>(l_xixcr_force_halt_cmd);
-        FAPI_TRY(fapi2::putScom(i_target, PU_GPE0_PPE_XIXCR, l_ppe_xixcr_data), "Error writing to GPE0 XIXCR register");
-        FAPI_TRY(fapi2::putScom(i_target, PU_GPE1_PPE_XIXCR, l_ppe_xixcr_data), "Error writing to GPE1 XIXCR register");
-        FAPI_TRY(fapi2::putScom(i_target, PU_GPE2_PPE_XIXCR, l_ppe_xixcr_data), "Error writing to GPE2 XIXCR register");
-        FAPI_TRY(fapi2::putScom(i_target, PU_GPE3_PPE_XIXCR, l_ppe_xixcr_data), "Error writing to GPE3 XIXCR register");
-
-        // SBE calls query_cache_access_state.C. For each Quad, if is_scomable then issue Halt to both CMEs in that Quad (ignoring core/EX partial good)
-        {
-            auto l_quad_functional_vector = i_target.getChildren<fapi2::TARGET_TYPE_EQ>(fapi2::TARGET_STATE_FUNCTIONAL);
-
-            for (auto quad_functional_it : l_quad_functional_vector)
+            if (!l_pgpe_in_safe_mode)
             {
-                bool l_l2_is_scomable = false;
-                bool l_l2_is_scanable = false;
-                bool l_l3_is_scomable = false;
-                bool l_l3_is_scanable = false;
 
-                FAPI_TRY(p9_query_cache_access_state(quad_functional_it, l_l2_is_scomable, l_l2_is_scanable, l_l3_is_scomable,
-                                                     l_l3_is_scanable), "Error getting cache access state");
+                l_occflg_data.flush<0>().setBit<p9hcd::PGPE_SAFE_MODE>();
+                FAPI_TRY(fapi2::putScom(i_target, PU_OCB_OCI_OCCFLG_SCOM2, l_occflg_data), "Error setting OCC Flag register bit 2");
 
-                if (l_l2_is_scomable && l_l3_is_scomable)
+                for (uint32_t i = 0; i < c_tries_before_timeout; i++)
                 {
-                    FAPI_TRY(fapi2::putScom(quad_functional_it, EQ_PPE_XIXCR, l_ppe_xixcr_data), "Error writing to the Quad's CME");
+                    FAPI_TRY(fapi2::getScom(i_target, PU_OCB_OCI_OCCS2_SCOM, l_occs2_data), "Error reading OCC Scratch 2 register");
+
+                    if(l_occs2_data.getBit<p9hcd::PGPE_SAFE_MODE_ACTIVE>())
+                    {
+                        l_pgpe_in_safe_mode = true;
+                        break;
+                    }
                 }
             }
-        }
 
-        // Clear PBA BARs 0-2 and disable PBA slaves 0-2 (DRTM paranoia to restore trust, but not BAR3 or Slave3 because SBE still needs memory access).
-        FAPI_TRY(fapi2::putScom(i_target, PU_PBABAR0, l_pba_data), "Error clearing PBABAR0");
-        FAPI_TRY(fapi2::putScom(i_target, PU_PBABAR1, l_pba_data), "Error clearing PBABAR1");
-        FAPI_TRY(fapi2::putScom(i_target, PU_PBABAR2, l_pba_data), "Error clearing PBABAR2");
-        FAPI_TRY(fapi2::putScom(i_target, PU_PBASLVCTL0_PIB, l_pba_data), "Error clearing PBASLVCTL0");
-        FAPI_TRY(fapi2::putScom(i_target, PU_PBASLVCTL1_PIB, l_pba_data), "Error clearing PBASLVCTL1");
-        FAPI_TRY(fapi2::putScom(i_target, PU_PBASLVCTL2_PIB, l_pba_data), "Error clearing PBASLVCTL2");
+            //TODO @todo RTC 164109 for when this is implemented in PGPE Hcode
+            /*FAPI_ASSERT(l_pgpe_in_safe_mode, fapi2::P9_PGPE_SAFEMODE_TIMEOUT().set_TARGET(i_target).set_OCCFLGREG(l_occflg_data),
+                        "PGPE did not set OCC Flag bit 6");
+            */
+            // In response, PGPE safe mode tell CME to go into safe mode.
+
+            // Suspend PGPE, SGPE, and CME from processing Pstate, WOF, and STOP entry/exit requests.
+            // (see above) Use OCC flag register bit 3 to request PM Complex suspend.:  In response, PGPE will stop processing Pstates, message SGPE to stop calling 24x7 thread andsuspend responding to Stop entry & exit. PGPE will message CME to stop processing Stop states??????.; then wait for ACK from each engine
+            l_occflg_data.flush<0>().setBit<p9hcd::PM_COMPLEX_SUSPEND>();
+            FAPI_TRY(fapi2::putScom(i_target, PU_OCB_OCI_OCCFLG_SCOM2, l_occflg_data), "Error setting OCC Flag register bit 3");
+            // TODO @todo RTC 164110 How to wait for ACK from each engine - an update is needed once the PGPE implements the function
+
+            // SBE would then issue the "halt OCC complex" (2 SCOMs) to stop OCC instructions (The "halt OCC complex" is that when it is removed the OCC complex won't start executing instructions. The prevent execution overrides any incoming start requests until released)
+            l_ocr_reg_data.setBit<PU_OCB_PIB_OCR_OCC_DBG_HALT>();
+            FAPI_TRY(fapi2::putScom(i_target, PU_OCB_PIB_OCR_OR, l_ocr_reg_data), "Error writing to OCR register");
+
+            // SBE then halts GPE0-3.
+            l_ppe_xixcr_data.insertFromRight<PU_GPE0_PPE_XIXCR_XCR, PU_GPE0_PPE_XIXCR_XCR_LEN>(l_xixcr_force_halt_cmd);
+            FAPI_TRY(fapi2::putScom(i_target, PU_GPE0_PPE_XIXCR, l_ppe_xixcr_data), "Error writing to GPE0 XIXCR register");
+            FAPI_TRY(fapi2::putScom(i_target, PU_GPE1_PPE_XIXCR, l_ppe_xixcr_data), "Error writing to GPE1 XIXCR register");
+            FAPI_TRY(fapi2::putScom(i_target, PU_GPE2_PPE_XIXCR, l_ppe_xixcr_data), "Error writing to GPE2 XIXCR register");
+            FAPI_TRY(fapi2::putScom(i_target, PU_GPE3_PPE_XIXCR, l_ppe_xixcr_data), "Error writing to GPE3 XIXCR register");
+
+            // SBE calls query_cache_access_state.C. For each Quad, if is_scomable then issue Halt to both CMEs in that Quad (ignoring core/EX partial good)
+            {
+                auto l_quad_functional_vector = i_target.getChildren<fapi2::TARGET_TYPE_EQ>(fapi2::TARGET_STATE_FUNCTIONAL);
+
+                for (auto quad_functional_it : l_quad_functional_vector)
+                {
+                    bool l_l2_is_scomable = false;
+                    bool l_l2_is_scanable = false;
+                    bool l_l3_is_scomable = false;
+                    bool l_l3_is_scanable = false;
+
+                    FAPI_TRY(p9_query_cache_access_state(quad_functional_it, l_l2_is_scomable, l_l2_is_scanable, l_l3_is_scomable,
+                                                         l_l3_is_scanable), "Error getting cache access state");
+
+                    if (l_l2_is_scomable && l_l3_is_scomable)
+                    {
+                        FAPI_TRY(fapi2::putScom(quad_functional_it, EQ_PPE_XIXCR, l_ppe_xixcr_data), "Error writing to the Quad's CME");
+                    }
+                }
+            }
+
+            // Clear PBA BARs 0-2 and disable PBA slaves 0-2 (DRTM paranoia to restore trust, but not BAR3 or Slave3 because SBE still needs memory access).
+            FAPI_TRY(fapi2::putScom(i_target, PU_PBABAR0, l_pba_data), "Error clearing PBABAR0");
+            FAPI_TRY(fapi2::putScom(i_target, PU_PBABAR1, l_pba_data), "Error clearing PBABAR1");
+            FAPI_TRY(fapi2::putScom(i_target, PU_PBABAR2, l_pba_data), "Error clearing PBABAR2");
+            FAPI_TRY(fapi2::putScom(i_target, PU_PBASLVCTL0_PIB, l_pba_data), "Error clearing PBASLVCTL0");
+            FAPI_TRY(fapi2::putScom(i_target, PU_PBASLVCTL1_PIB, l_pba_data), "Error clearing PBASLVCTL1");
+            FAPI_TRY(fapi2::putScom(i_target, PU_PBASLVCTL2_PIB, l_pba_data), "Error clearing PBASLVCTL2");
+
+        } // if (0) - see the @todo RTC 147282
+
 
     fapi_try_exit:
         FAPI_DBG("Exiting...");