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| author | Ben Gass <bgass@us.ibm.com> | 2017-05-10 08:03:21 -0500 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2017-07-14 00:40:28 -0400 |
| commit | 05a9caf05f0ed3c497364d82b994e6645b37c8bd (patch) | |
| tree | a9b2d6bac51a5636b28a0d7ac49831182e79b7f9 /src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.C | |
| parent | 0c98c6972a545a5563daeeb0e582e90b1d3a1b90 (diff) | |
| download | talos-sbe-05a9caf05f0ed3c497364d82b994e6645b37c8bd.tar.gz talos-sbe-05a9caf05f0ed3c497364d82b994e6645b37c8bd.zip | |
Create dmi.pll.scan.initfile
Support sync and async mode for Cumulus MC
Default buckets are 1.
Change-Id: I62d0221abf7f93030cb8c0200a456609ab4dfe04
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40326
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Benjamin Gass <bgass@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41056
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.C')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.C | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.C index 9c255adb..71b672aa 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.C @@ -84,6 +84,7 @@ fapi2::ReturnCode p9_sbe_chiplet_pll_setup(const { uint8_t l_read_attr = 0; uint8_t l_bypass = 0; + uint8_t l_use_dmi_buckets = 0; FAPI_INF("p9_sbe_chiplet_pll_setup: Entering ..."); auto l_mc_io_func = i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>( @@ -92,6 +93,9 @@ fapi2::ReturnCode p9_sbe_chiplet_pll_setup(const fapi2::TARGET_FILTER_ALL_PCI), fapi2::TARGET_STATE_FUNCTIONAL); + FAPI_DBG("Read ATTR_CHIP_EC_FEATURE_DMI_MC_PLL_SCAN_BUCKETS "); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_DMI_MC_PLL_SCAN_BUCKETS, i_target_chip, l_use_dmi_buckets)); + FAPI_DBG("Reading bypass attribute"); FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_NEST_MEM_X_O_PCI_BYPASS, i_target_chip, l_bypass)); @@ -107,7 +111,7 @@ fapi2::ReturnCode p9_sbe_chiplet_pll_setup(const FAPI_DBG("Drop PDLY bypass"); FAPI_TRY(p9_sbe_chiplet_pll_setup_mc_pdly_dcc_bypass(mc, true, false)); - if ( !(l_read_attr) ) + if ( !(l_read_attr) || l_use_dmi_buckets ) { FAPI_DBG("Drop DCC bypass"); FAPI_TRY(p9_sbe_chiplet_pll_setup_mc_pdly_dcc_bypass(mc, false, true)); @@ -135,7 +139,7 @@ fapi2::ReturnCode p9_sbe_chiplet_pll_setup(const uint32_t l_chipletID = targ.getChipletNumber(); if(l_chipletID == XB_CHIPLET_ID || (l_chipletID >= OB0_CHIPLET_ID && l_chipletID <= OB3_CHIPLET_ID) || - ((!l_read_attr) && (l_chipletID == MC01_CHIPLET_ID || l_chipletID == MC23_CHIPLET_ID)) ) + ((!l_read_attr || l_use_dmi_buckets) && (l_chipletID == MC01_CHIPLET_ID || l_chipletID == MC23_CHIPLET_ID)) ) { FAPI_DBG("release pll test enable for except pcie"); FAPI_TRY(p9_sbe_chiplet_pll_setup_pll_test_enable(targ)); @@ -149,7 +153,7 @@ fapi2::ReturnCode p9_sbe_chiplet_pll_setup(const if(l_chipletID == XB_CHIPLET_ID || (l_chipletID >= OB0_CHIPLET_ID && l_chipletID <= OB3_CHIPLET_ID) || (l_chipletID >= PCI0_CHIPLET_ID && l_chipletID <= PCI2_CHIPLET_ID) || - ((!l_read_attr) && (l_chipletID == MC01_CHIPLET_ID || l_chipletID == MC23_CHIPLET_ID)) ) + ((!l_read_attr || l_use_dmi_buckets) && (l_chipletID == MC01_CHIPLET_ID || l_chipletID == MC23_CHIPLET_ID)) ) { FAPI_DBG("Release PLL reset"); FAPI_TRY(p9_sbe_chiplet_pll_setup_pll_reset(targ)); @@ -174,7 +178,7 @@ fapi2::ReturnCode p9_sbe_chiplet_pll_setup(const uint32_t l_chipletID = targ.getChipletNumber(); if(l_chipletID == XB_CHIPLET_ID || (l_chipletID >= OB0_CHIPLET_ID && l_chipletID <= OB3_CHIPLET_ID) || - ((!l_read_attr) && (l_chipletID == MC01_CHIPLET_ID || l_chipletID == MC23_CHIPLET_ID)) ) + ((!l_read_attr || l_use_dmi_buckets) && (l_chipletID == MC01_CHIPLET_ID || l_chipletID == MC23_CHIPLET_ID)) ) { FAPI_DBG("check pll lock for Mc,Xb,Ob"); FAPI_TRY(p9_sbe_chiplet_pll_setup_check_pll_lock(targ, false)); @@ -189,7 +193,7 @@ fapi2::ReturnCode p9_sbe_chiplet_pll_setup(const if(l_chipletID == XB_CHIPLET_ID || (l_chipletID >= OB0_CHIPLET_ID && l_chipletID <= OB3_CHIPLET_ID) || (l_chipletID >= PCI0_CHIPLET_ID && l_chipletID <= PCI2_CHIPLET_ID) || - ((!l_read_attr) && (l_chipletID == MC01_CHIPLET_ID || l_chipletID == MC23_CHIPLET_ID)) ) + ((!l_read_attr || l_use_dmi_buckets) && (l_chipletID == MC01_CHIPLET_ID || l_chipletID == MC23_CHIPLET_ID)) ) { FAPI_TRY(p9_sbe_chiplet_pll_setup_function(targ, l_bypass)); } |
