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| author | Jin Song Jiang <jjsjiang@cn.ibm.com> | 2017-04-21 11:47:20 -0500 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2017-06-01 05:03:57 -0400 |
| commit | 1c7ae19b4fa7b36e7aac0c3401dcc5d93790c442 (patch) | |
| tree | 94383c63cded98f6e2041a7622989136133716d0 /src/import/chips/p9/common/include/p9_mc_scom_addresses_fixes.H | |
| parent | 6ec048d4f32dadedeff505f9a0cfa4a37ce541df (diff) | |
| download | talos-sbe-1c7ae19b4fa7b36e7aac0c3401dcc5d93790c442.tar.gz talos-sbe-1c7ae19b4fa7b36e7aac0c3401dcc5d93790c442.zip | |
p9_cen_framelock -- 2nd version
1) Replace MCSMODE4 register with MCMODE2 and MCBCFGQ register
shift host attention enablement to p9c_set_inband_addr HWP
2) Update FIR registers'(ACT0,ACT1 and MASK) set from p8 to p9c
Change-Id: Ifdce2d948c12ad2b82a74cfc6a8731617a3086df
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39558
Dev-Ready: Brent Wieman <bwieman@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39560
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import/chips/p9/common/include/p9_mc_scom_addresses_fixes.H')
| -rw-r--r-- | src/import/chips/p9/common/include/p9_mc_scom_addresses_fixes.H | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/src/import/chips/p9/common/include/p9_mc_scom_addresses_fixes.H b/src/import/chips/p9/common/include/p9_mc_scom_addresses_fixes.H index d78c69ff..6b1ff94e 100644 --- a/src/import/chips/p9/common/include/p9_mc_scom_addresses_fixes.H +++ b/src/import/chips/p9/common/include/p9_mc_scom_addresses_fixes.H @@ -43,6 +43,32 @@ REG64( MCA_MBA_MCP0XLT0 , RULL(0x05010820), REG64( MCA_MBA_MCP0XLT1 , RULL(0x05010821), SH_UNT_MCA , SH_ACS_SCOM_RW ); REG64( MCA_MBA_MCP0XLT2 , RULL(0x05010822), SH_UNT_MCA , SH_ACS_SCOM_RW ); +// Register define for Framelock +REG64( DMI_DATAPATHFIR_0x07010900 , RULL(0x07010900), SH_UNT_MCA , + SH_ACS_SCOM_RW ); +REG64( DMI_DATAPATHFIR_AND_0x07010901 , RULL(0x07010901), SH_UNT_MCA , + SH_ACS_SCOM1_AND ); +REG64( DMI_DATAPATHFIR_OR_0x07010902 , RULL(0x07010902), SH_UNT_MCA , + SH_ACS_SCOM2_OR ); +REG64( DMI_DATAPATHFIRMASK_0x07010903 , RULL(0x07010903), SH_UNT_MCA , + SH_ACS_SCOM_RW ); +REG64( DMI_DATAPATHFIRMASK_AND_0x07010904 , RULL(0x07010904), SH_UNT_MCA , + SH_ACS_SCOM1_AND ); +REG64( DMI_DATAPATHFIRMASK_OR_0x07010905 , RULL(0x07010905), SH_UNT_MCA , + SH_ACS_SCOM2_OR ); +REG64( DMI_DATAPATHFIRACT0_0x07010906 , RULL(0x07010906), SH_UNT_MCA , + SH_ACS_SCOM ); +REG64( DMI_DATAPATHFIRACT1_0x07010907 , RULL(0x07010907), SH_UNT_MCA , + SH_ACS_SCOM ); +REG64( DMI_MCICFG_0x0701090A , RULL(0x0701090A), SH_UNT_MCA , + SH_ACS_SCOM ); +REG64( DMI_MCISTAT_0x0701090B , RULL(0x0701090B), SH_UNT_MCA , + SH_ACS_SCOM ); +REG64( MI_MCMODE2_0x05010813 , RULL(0x05010813), SH_UNT_MCA , + SH_ACS_SCOM ); +REG64( DMI_MCBCFG_0x070123E0 , RULL(0x070123E0), SH_UNT_MCA , + SH_ACS_SCOM ); + // DDRPHY registers renamed in DD2.0 REG64( MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_0 , RULL(0x800000160701103F), SH_UNT_MCA , SH_ACS_SCOM_RW ); |
