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| author | Dean Sanner <dsanner@us.ibm.com> | 2017-07-17 08:21:44 -0500 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2017-07-17 22:21:48 -0400 |
| commit | 58ee9463a7c31f9bcaf0c60f5c429906e66bf660 (patch) | |
| tree | 5a2730ec65be84a85302043f1bf12aaac96b09da /src/boot | |
| parent | 5fc238e822ae4123f6a2504cdad3136b149fde7b (diff) | |
| download | talos-sbe-58ee9463a7c31f9bcaf0c60f5c429906e66bf660.tar.gz talos-sbe-58ee9463a7c31f9bcaf0c60f5c429906e66bf660.zip | |
Have SBE set PSSCR in fused core mode
- PM team added code to honor the "enable state loss" bits
- This broke istep 16, as threads 2,3 PSSCR values default to 0s
- This commit fixes it by setting a default value in threads 2,
3. Note that the SBE is the only place to do this, as HB
cannot RAM the PSSCR of the stopped threads since it is running
on threads 0,1
Change-Id: Ia861be3f1f303f9f2750d306803091220b66e084
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43206
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43207
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/boot')
0 files changed, 0 insertions, 0 deletions
