Reg access support

RTC: 128984
Change-Id: I6c5637de94077cca58a72d20a88c6db20c137632
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/22279
Tested-by: Jenkins Server
Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
Reviewed-by: AMIT J. TENDOLKAR <amit.tendolkar@in.ibm.com>

19 files changed, 1509 insertions, 2 deletions

diff --git a/sbe/build/citest/etc/patches/chip.act.patch b/sbe/build/citest/etc/patches/chip.act.patch
new file mode 100644
index 00000000..4e47f2fc
--- /dev/null
+++ b/sbe/build/citest/etc/patches/chip.act.patch
@@ -0,0 +1,2 @@
+265a266
+>   EFFECT: TARGET=[MODULE(executeInstruction, MYCORE)] OP=[MODULECALL] DATA=[REG(MYCHIPLET, 0x00010A4F)]
diff --git a/sbe/build/citest/etc/patches/p9.inst.patch b/sbe/build/citest/etc/patches/p9.inst.patch
new file mode 100644
index 00000000..eba2f47d
--- /dev/null
+++ b/sbe/build/citest/etc/patches/p9.inst.patch
@@ -0,0 +1,880 @@
+6c6,10
+< 
+---
+> # This file maps ppc core instructions to simics instructions.
+> # First column tells the ppc instruction. The rest of columns
+> # indicates the corrosponding  simics instruction. Simics
+> # only support single thread. So all instructions are for thread0.
+> # For ppc instructions refer to PPC instruction set architecture(ISA).
+13,180c17,184
+< 0F821F54C0000000, mv, hid0, gpr0
+< 0F821F74C0000000, mv, gpr0, hid0
+< 0F832954C0000000, mv, hrmor, gpr0
+< 0F832974C0000000, mv, gpr0, hrmor
+< 0F806054C0000000, mv, dscr, gpr0
+< 0F806074C0000000, mv, gpr0, dscr 
+< 0F81A054C0000000, mv, uamr, gpr0
+< 0F81A074C0000000, mv, gpr0, uamr
+< 0F83A154C0000000, mv, iamr, gpr0
+< 0F83A174C0000000, mv, gpr0, iamr
+< 0F800454C0000000, mv, tfhar, gpr0
+< 0F800474C0000000, mv, gpr0, tfhar
+< 0F804454C0000000, mv, texasr, gpr0
+< 0F804474C0000000, mv, gpr0, texasr
+< 0F806454C0000000, mv, texasru, gpr0
+< 0F806474C0000000, mv, gpr0, texasru
+< 0F814454C0000000, mv, apscr, gpr0
+< 0F814474C0000000, mv, gpr0, apscr
+< 0F816454C0000000, mv, apscru, gpr0 
+< 0F816474C0000000, mv, gpr0, apscru
+< 0F820454C0000000, mv, tidr, gpr0
+< 0F820474C0000000, mv, gpr0, tidr
+< 0F832454C0000000, mv, fscr, gpr0
+< 0F832474C0000000, mv, gpr0, fscr
+< 0F83E454C0000000, mv, pspb, gpr0
+< 0F83E474C0000000, mv, gpr0, pspb
+< 0F820554C0000000, mv, dpdes, gpr0
+< 0F820574C0000000, mv, gpr0, dpdes
+< 0F822554C0000000, mv, dhdes, gpr0
+< 0F822574C0000000, mv, gpr0, dhdes
+< 0F828554C0000000, mv, dawr, gpr0
+< 0F828574C0000000, mv, gpr0, dawr
+< 0F830554C0000000, mv, mppr, gpr0
+< 0F830574C0000000, mv, gpr0, mppr
+< 0F834554C0000000, mv, rpr, gpr0
+< 0F834574C0000000, mv, gpr0, rpr
+< 0F836554C0000000, mv, ciabr, gpr0
+< 0F836574C0000000, mv, gpr0, ciabr
+< 0F838554C0000000, mv, dawrx, gpr0
+< 0F838574C0000000, mv, gpr0, dawrx
+< 0F83C554C0000000, mv, hfscr, gpr0
+< 0F83C574C0000000, mv, gpr0, hfscr
+< 0F828854C0000000, mv, sprc, gpr0
+< 0F828874C0000000, mv, gpr0, sprc
+< 0F836854C0000000, mv, cir, gpr0
+< 0F836874C0000000, mv, gpr0, cir
+< 0F83EA54C0000000, mv, hacop, gpr0
+< 0F83EA74C0000000, mv, gpr0, hacop
+< 0F83C854C0000000, mv, tbu40, gpr0
+< 0F83C874C0000000, mv, gpr0, tbu40
+< 0F83E854C0000000, mv, pvr, gpr0
+< 0F83E874C0000000, mv, gpr0, pvr
+< 0F82A954C0000000, mv, purr, gpr0
+< 0F82A974C0000000, mv, gpr0, purr
+< 0F830954C0000000, mv, rmor, gpr0
+< 0F830974C0000000, mv, gpr0, rmor 
+< 0F83CD54C0000000, mv, tir, gpr0
+< 0F83CD74C0000000, mv, gpr0, tir
+< 0F821854C0000000, mv, sier, gpr0
+< 0F821874C0000000, mv, gpr0, sier
+< 0F823854C0000000, mv, mmcr2, gpr0
+< 0F823874C0000000, mv, gpr0, mmcr2
+< 0F83F854C0000000, mv, imc, gpr0
+< 0F83F874C0000000, mv, gpr0, imc
+< 0F801954C0000000, mv, bescrs, gpr0
+< 0F801974C0000000, mv, gpr0, bescrs
+< 0F803954C0000000, mv, bescrsu, gpr0
+< 0F803974C0000000, mv, gpr0, bescrsu
+< 0F805954C0000000, mv, bescrr, gpr0
+< 0F805974C0000000, mv, gpr0, bescrr
+< 0F807954C0000000, mv, bescrru, gpr0
+< 0F807974C0000000, mv, gpr0, bescrru
+< 0F809954C0000000, mv, ebbhr, gpr0
+< 0F809974C0000000, mv, gpr0, ebbhr
+< 0F80B954C0000000, mv, ebbrr, gpr0
+< 0F80B974C0000000, mv, gpr0, ebbrr
+< 0F80D954C0000000, mv, bescrr, gpr0
+< 0F80D974C0000000, mv, gpr0, bescrr
+< 0F81F954C0000000, mv, tar, gpr0
+< 0F81F974C0000000, mv, gpr0, tar
+< 0F821A54C0000000, mv, ic, gpr0
+< 0F821A74C0000000, mv, gpr0, ic
+< 0F823A54C0000000, mv, vtb, gpr0
+< 0F823A74C0000000, mv, gpr0, vtb
+< 0F825A54C0000000, mv, ldbar, gpr0
+< 0F825A74C0000000, mv, gpr0, ldbar
+< 0F827A54C0000000, mv, mmcrc, gpr0
+< 0F827A74C0000000, mv, gpr0, mmcrc
+< 0F829A54C0000000, mv, pmicr, gpr0
+< 0F829A74C0000000, mv, gpr0, pmicr
+< 0F82BA54C0000000, mv, pmsr, gpr0
+< 0F82BA74C0000000, mv, gpr0, pmsr
+< 0F82DA54C0000000, mv, pmmar, gpr0
+< 0F82DA74C0000000, mv, gpr0, pmmar
+< 0F83FA54C0000000, mv, worc, gpr0
+< 0F83FA74C0000000, mv, gpr0, worc
+< 0F831B54C0000000, mv, tacr, gpr0
+< 0F831B74C0000000, mv, gpr0, tacr
+< 0F833B54C0000000, mv, tcscr, gpr0
+< 0F833B74C0000000, mv, gpr0, tcscr
+< 0F835B54C0000000, mv, csigr, gpr0
+< 0F835B74C0000000, mv, gpr0, csigr
+< 0F839B54C0000000, mv, spcm1, gpr0
+< 0F839B74C0000000, mv, gpr0, spcm1
+< 0F83BB54C0000000, mv, spcm2, gpr0
+< 0F83BB74C0000000, mv, gpr0, spcm2
+< 0F83DB54C0000000, mv, mmcrs, gpr0
+< 0F83DB74C0000000, mv, gpr0, mmcrs
+< 0F83FB54C0000000, mv, wort, gpr0
+< 0F83FB74C0000000, mv, gpr0, wort
+< 0F805C54C0000000, mv, ppr32, gpr0
+< 0F805C74C0000000, mv, gpr0, ppr32
+< 0F803C54C0000000, mv, tsr, gpr0
+< 0F803C74C0000000, mv, gpr0, tsr
+< 0F835C54C0000000, mv, ttr, gpr0
+< 0F835C74C0000000, mv, gpr0, ttr
+< 0F81DF54C0000000, mv, trace, gpr0
+< 0F81DF74C0000000, mv, gpr0, trace
+< 0F83E054C0000000, mv, acop, gpr0
+< 0F83E074C0000000, mv, gpr0, acop
+< 0F83AA54C0000000, mv, amor, gpr0
+< 0F83AA74C0000000, mv, gpr0, amor
+< 0F83A054C0000000, mv, amr, gpr0
+< 0F83A074C0000000, mv, gpr0, amr
+< 0F838054C0000000, mv, cfar, gpr0
+< 0F838074C0000000, mv, gpr0, cfar
+< 0F820204C0000000, mv, cr0, gpr0
+< 0F82022400000000, mv, gpr0, cr0
+< 0F820404C0000000, mv, cr1, gpr0
+< 0F82042400000000, mv, gpr0, cr1
+< 0F820804C0000000, mv, cr2, gpr0
+< 0F82082400000000, mv, gpr0, cr2
+< 0F821004C0000000, mv, cr3, gpr0
+< 0F82102400000000, mv, gpr0, cr3
+< 0F822004C0000000, mv, cr4, gpr0
+< 0F82202400000000, mv, gpr0, cr4
+< 0F824004C0000000, mv, cr5, gpr0
+< 0F82402400000000, mv, gpr0, cr5
+< 0F828004C0000000, mv, cr6, gpr0
+< 0F82802400000000, mv, gpr0, cr6
+< 0F830004C0000000, mv, cr7, gpr0
+< 0F83002400000000, mv, gpr0, cr7
+< 0F812054C0000000, mv, ctr, gpr0
+< 0F812074C0000000, mv, gpr0, ctr
+< 0F830454C0000000, mv, ctrl, gpr0
+< 0F830474C0000000, mv, gpr0, ctrl  #@06
+< 0F82BF54C0000000, mv, dabr, gpr0
+< 0F82BF74C0000000, mv, gpr0, dabr
+< 0F82FF54C0000000, mv, dabrx, gpr0
+< 0F82FF74C0000000, mv, gpr0, dabrx
+< 0F826054C0000000, mv, dar, gpr0
+< 0F826074C0000000, mv, gpr0, dar
+< 0F835D54C0000000, mv, dcidr0, gpr0
+< 0F835D74C0000000, mv, gpr0, dcidr0
+< 0F83BD54C0000000, mv, dcidr1, gpr0
+< 0F83BD74C0000000, mv, gpr0, dcidr1
+< 0F82C054C0000000, mv, dec, gpr0
+< 0F82C074C0000000, mv, gpr0, dec
+< 0F833D54C0000000, mv, drmr0, gpr0
+< 0F833D74C0000000, mv, gpr0, drmr0
+< 0F839D54C0000000, mv, drmr1, gpr0
+< 0F839D74C0000000, mv, gpr0, drmr1
+< 0F831D54C0000000, mv, drsr0, gpr0
+< 0F831D74c0000000, mv, gpr0, drsr0
+< 0F837D54C0000000, mv, drsr1, gpr0
+< 0F837D74C0000000, mv, gpr0, drsr1
+< 0F824054C0000000, mv, dsisr, gpr0
+< 0F824074C0000000, mv, gpr0, dsisr
+---
+> 007c10faa6000000, mv, hid0, gpr0
+> 007c10fba6000000, mv, gpr0, hid0
+> 007c194aa6000000, mv, hrmor, gpr0
+> 007c194ba6000000, mv, gpr0, hrmor
+> 007c0302a6000000, mv, dscr, gpr0
+> 007c0303a6000000, mv, gpr0, dscr 
+> 007c0d02a6000000, mv, uamr, gpr0
+> 007c0d03a6000000, mv, gpr0, uamr
+> 007c1d0aa6000000, mv, iamr, gpr0
+> 007c1d0ba6000000, mv, gpr0, iamr
+> 007c0022a6000000, mv, tfhar, gpr0
+> 007c0023a6000000, mv, gpr0, tfhar
+> 007c0222a6000000, mv, texasr, gpr0
+> 007c0223a6000000, mv, gpr0, texasr
+> 007c0322a6000000, mv, texasru, gpr0
+> 007c0323a6000000, mv, gpr0, texasru
+> 007c0a22a6000000, mv, apscr, gpr0
+> 007c0a23a6000000, mv, gpr0, apscr
+> 007c0b22a6000000, mv, apscru, gpr0 
+> 007c0b23a6000000, mv, gpr0, apscru
+> 007c1022a6000000, mv, tidr, gpr0
+> 007c1023a6000000, mv, gpr0, tidr
+> 007c1922a6000000, mv, fscr, gpr0
+> 007c1923a6000000, mv, gpr0, fscr
+> 007c1f22a6000000, mv, pspb, gpr0
+> 007c1f23a6000000, mv, gpr0, pspb
+> 007c102aa6000000, mv, dpdes, gpr0
+> 007c102ba6000000, mv, gpr0, dpdes
+> 007c112aa6000000, mv, dhdes, gpr0
+> 007c112ba6000000, mv, gpr0, dhdes
+> 007c142aa6000000, mv, dawr, gpr0
+> 007c142ba6000000, mv, gpr0, dawr
+> 007c182aa6000000, mv, mppr, gpr0
+> 007c182ba6000000, mv, gpr0, mppr
+> 007c1a2aa6000000, mv, rpr, gpr0
+> 007c1a2ba6000000, mv, gpr0, rpr
+> 007c1b2aa6000000, mv, ciabr, gpr0
+> 007c1b2ba6000000, mv, gpr0, ciabr
+> 007c1c2aa6000000, mv, dawrx, gpr0
+> 007c1c2ba6000000, mv, gpr0, dawrx
+> 007c1e2aa6000000, mv, hfscr, gpr0
+> 007c1e2ba6000000, mv, gpr0, hfscr
+> 007c1442a6000000, mv, sprc, gpr0
+> 007c1443a6000000, mv, gpr0, sprc
+> 007c1b42a6000000, mv, cir, gpr0
+> 007c1b43a6000000, mv, gpr0, cir
+> 007c1f52a6000000, mv, hacop, gpr0
+> 007c1f53a6000000, mv, gpr0, hacop
+> 007c1e42a6000000, mv, tbu40, gpr0
+> 007c1e43a6000000, mv, gpr0, tbu40
+> 007c1f42a6000000, mv, pvr, gpr0
+> 007c1f43a6000000, mv, gpr0, pvr
+> 007c154aa6000000, mv, purr, gpr0
+> 007c154ba6000000, mv, gpr0, purr
+> 007c184aa6000000, mv, rmor, gpr0
+> 007c184ba6000000, mv, gpr0, rmor 
+> 007c1e6aa6000000, mv, tir, gpr0
+> 007c1e6ba6000000, mv, gpr0, tir
+> 007c10c2a6000000, mv, sier, gpr0
+> 007c10c3a6000000, mv, gpr0, sier
+> 007c11c2a6000000, mv, mmcr2, gpr0
+> 007c11c3a6000000, mv, gpr0, mmcr2
+> 007c1fc2a6000000, mv, imc, gpr0
+> 007c1fc3a6000000, mv, gpr0, imc
+> 007c00caa6000000, mv, bescrs, gpr0
+> 007c00cba6000000, mv, gpr0, bescrs
+> 007c01caa6000000, mv, bescrsu, gpr0
+> 007c01cba6000000, mv, gpr0, bescrsu
+> 007c02caa6000000, mv, bescrr, gpr0
+> 007c02cba6000000, mv, gpr0, bescrr
+> 007c03caa6000000, mv, bescrru, gpr0
+> 007c03cba6000000, mv, gpr0, bescrru
+> 007c04caa6000000, mv, ebbhr, gpr0
+> 007c04cba6000000, mv, gpr0, ebbhr
+> 007c05caa6000000, mv, ebbrr, gpr0
+> 007c05cba6000000, mv, gpr0, ebbrr
+> 007c06caa6000000, mv, bescrr, gpr0
+> 007c06cba6000000, mv, gpr0, bescrr
+> 007c0fcaa6000000, mv, tar, gpr0
+> 007c0fcba6000000, mv, gpr0, tar
+> 007c10d2a6000000, mv, ic, gpr0
+> 007c10d3a6000000, mv, gpr0, ic
+> 007c11d2a6000000, mv, vtb, gpr0
+> 007c11d3a6000000, mv, gpr0, vtb
+> 007c12d2a6000000, mv, ldbar, gpr0
+> 007c12d3a6000000, mv, gpr0, ldbar
+> 007c13d2a6000000, mv, mmcrc, gpr0
+> 007c13d3a6000000, mv, gpr0, mmcrc
+> 007c14d2a6000000, mv, pmicr, gpr0
+> 007c14d3a6000000, mv, gpr0, pmicr
+> 007c15d2a6000000, mv, pmsr, gpr0
+> 007c15d3a6000000, mv, gpr0, pmsr
+> 007c16d2a6000000, mv, pmmar, gpr0
+> 007c16d3a6000000, mv, gpr0, pmmar
+> 007c1fd2a6000000, mv, worc, gpr0
+> 007c1fd3a6000000, mv, gpr0, worc
+> 007c18daa6000000, mv, tacr, gpr0
+> 007c18dba6000000, mv, gpr0, tacr
+> 007c19daa6000000, mv, tcscr, gpr0
+> 007c19dba6000000, mv, gpr0, tcscr
+> 007c1adaa6000000, mv, csigr, gpr0
+> 007c1adba6000000, mv, gpr0, csigr
+> 007c1cdaa6000000, mv, spcm1, gpr0
+> 007c1cdba6000000, mv, gpr0, spcm1
+> 007c1ddaa6000000, mv, spcm2, gpr0
+> 007c1ddba6000000, mv, gpr0, spcm2
+> 007c1edaa6000000, mv, mmcrs, gpr0
+> 007c1edba6000000, mv, gpr0, mmcrs
+> 007c1fdaa6000000, mv, wort, gpr0
+> 007c1fdba6000000, mv, gpr0, wort
+> 007c02e2a6000000, mv, ppr32, gpr0
+> 007c02e3a6000000, mv, gpr0, ppr32
+> 007c01e2a6000000, mv, tsr, gpr0
+> 007c01e3a6000000, mv, gpr0, tsr
+> 007c1ae2a6000000, mv, ttr, gpr0
+> 007c1ae3a6000000, mv, gpr0, ttr
+> 007c0efaa6000000, mv, trace, gpr0
+> 007c0efba6000000, mv, gpr0, trace
+> 007c1f02a6000000, mv, acop, gpr0
+> 007c1f03a6000000, mv, gpr0, acop
+> 007c1d52a6000000, mv, amor, gpr0
+> 007c1d53a6000000, mv, gpr0, amor
+> 007c1d02a6000000, mv, amr, gpr0
+> 007c1d03a6000000, mv, gpr0, amr
+> 007c1c02a6000000, mv, cfar, gpr0
+> 007c1c03a6000000, mv, gpr0, cfar
+> 007c101026000000, mv, cr0, gpr0
+> 007c101120000000, mv, gpr0, cr0
+> 007c102026000000, mv, cr1, gpr0
+> 007c102120000000, mv, gpr0, cr1
+> 007c104026000000, mv, cr2, gpr0
+> 007c104120000000, mv, gpr0, cr2
+> 007c108026000000, mv, cr3, gpr0
+> 007c108120000000, mv, gpr0, cr3
+> 007c110026000000, mv, cr4, gpr0
+> 007c110120000000, mv, gpr0, cr4
+> 007c120026000000, mv, cr5, gpr0
+> 007c120120000000, mv, gpr0, cr5
+> 007c140026000000, mv, cr6, gpr0
+> 007c140120000000, mv, gpr0, cr6
+> 007c180026000000, mv, cr7, gpr0
+> 007c180120000000, mv, gpr0, cr7
+> 007c0902a6000000, mv, ctr, gpr0
+> 007c0903a6000000, mv, gpr0, ctr
+> 007c1822a6000000, mv, ctrl, gpr0
+> 007c1823a6000000, mv, gpr0, ctrl  #@06
+> 007c15faa6000000, mv, dabr, gpr0
+> 007c15fba6000000, mv, gpr0, dabr
+> 007c17faa6000000, mv, dabrx, gpr0
+> 007c17fba6000000, mv, gpr0, dabrx
+> 007c1302a6000000, mv, dar, gpr0
+> 007c1303a6000000, mv, gpr0, dar
+> 007c1aeaa6000000, mv, dcidr0, gpr0
+> 007c1aeba6000000, mv, gpr0, dcidr0
+> 007c1deaa6000000, mv, dcidr1, gpr0
+> 007c1deba6000000, mv, gpr0, dcidr1
+> 007c1602a6000000, mv, dec, gpr0
+> 007c1603a6000000, mv, gpr0, dec
+> 007c19eaa6000000, mv, drmr0, gpr0
+> 007c19eba6000000, mv, gpr0, drmr0
+> 007c1ceaa6000000, mv, drmr1, gpr0
+> 007c1ceba6000000, mv, gpr0, drmr1
+> 007c18eaa6000000, mv, drsr0, gpr0
+> 007c18eba6000000, mv, gpr0, drsr0
+> 007c1beaa6000000, mv, drsr1, gpr0
+> 007c1beba6000000, mv, gpr0, drsr1
+> 007c1202a6000000, mv, dsisr, gpr0
+> 007c1203a6000000, mv, gpr0, dsisr
+183,243c187,247
+< 0F826954C0000000, mv, hdar, gpr0
+< 0F826974C0000000, mv, gpr0, hdar
+< 0F82C954C0000000, mv, hdec, gpr0
+< 0F82C974C0000000, mv, gpr0, hdec
+< 0F824954C0000000, mv, hdsisr, gpr0
+< 0F824974C0000000, mv, gpr0, hdsisr
+< 0F826A54C0000000, mv, heir, gpr0
+< 0F826A74C0000000, mv, gpr0, heir
+< 0F823F54C0000000, mv, hid1, gpr0
+< 0F823F74C0000000, mv, gpr0, hid1
+< 0F829F54C0000000, mv, hid4, gpr0
+< 0F829F74C0000000, mv, gpr0, hid4
+< 0F82DF54C0000000, mv, hid5, gpr0
+< 0F82DF74C0000000, mv, gpr0, hid5
+< 0F822A54C0000000, mv, hmeer, gpr0
+< 0F822A74C0000000, mv, gpr0, hmeer
+< 0F820A54C0000000, mv, hmer, gpr0
+< 0F820A74C0000000, mv, gpr0, hmer
+< 0F830A54C0000000, mv, hpmc1, gpr0
+< 0F830A74C0000000, mv, gpr0, hpmc1
+< 0F832A54C0000000, mv, hpmc2, gpr0
+< 0F832A74C0000000, mv, gpr0, hpmc2
+< 0F834A54C0000000, mv, hpmc3, gpr0
+< 0F834A74C0000000, mv, gpr0, hpmc3
+< 0F836A54C0000000, mv, hpmc4, gpr0
+< 0F836A74C0000000, mv, gpr0, hpmc4
+< 0F820954C0000000, mv, hsprg0, gpr0
+< 0F820974C0000000, mv, gpr0, hsprg0
+< 0F822954C0000000, mv, hsprg1, gpr0
+< 0F822974C0000000, mv, gpr0, hsprg1
+< 0F834954C0000000, mv, hsrr0, gpr0
+< 0F834974C0000000, mv, gpr0, hsrr0
+< 0F836954C0000000, mv, hsrr1, gpr0
+< 0F836974C0000000, mv, gpr0, hsrr1
+< f825e54c0000000, mv, icidr0, gpr0
+< f825e74c0000000, mv, gpr0, icidr0
+< f82be54c0000000, mv, icidr1, gpr0
+< f82be74c0000000, mv, gpr0, icidr1
+< f823e54c0000000, mv, irmr0, gpr0
+< f823e74c0000000, mv, gpr0, irmr0
+< f829e54c0000000, mv, irmr1, gpr0
+< f829e74c0000000, mv, gpr0, irmr1
+< f821e54c0000000, mv, irsr0, gpr0
+< f821e74c0000000, mv, gpr0, irsr0
+< f827e54c0000000, mv, irsr1, gpr0
+< f827e74c0000000, mv, gpr0, irsr1
+< 0F83C954C0000000, mv, lpcr, gpr0
+< 0F83C974C0000000, mv, gpr0, lpcr
+< 0F83E954C0000000, mv, lpidr, gpr0
+< 0F83E974C0000000, mv, gpr0, lpidr
+< 0F810054C0000000, mv, lr, gpr0
+< 0F810074C0000000, mv, gpr0, lr
+< 0F837854C0000000, mv, mmcr0, gpr0
+< 0F837874C0000000, mv, gpr0, mmcr0
+< 0F83D854C0000000, mv, mmcr1, gpr0
+< 0F83D874C0000000, mv, gpr0, mmcr1
+< 0F825854C0000000, mv, mmcra, gpr0
+< 0F825874C0000000, mv, gpr0, mmcra
+< 0F838954C0000000, mv, mmcrh, gpr0
+< 0F838974C0000000, mv, gpr0, mmcrh
+< 0F800014C0000000, mv, msr, gpr0
+---
+> 007c134aa6000000, mv, hdar, gpr0
+> 007c134ba6000000, mv, gpr0, hdar
+> 007c164aa6000000, mv, hdec, gpr0
+> 007c164ba6000000, mv, gpr0, hdec
+> 007c124aa6000000, mv, hdsisr, gpr0
+> 007c124ba6000000, mv, gpr0, hdsisr
+> 007c1352a6000000, mv, heir, gpr0
+> 007c1353a6000000, mv, gpr0, heir
+> 007c11faa6000000, mv, hid1, gpr0
+> 007c11fba6000000, mv, gpr0, hid1
+> 007c14faa6000000, mv, hid4, gpr0
+> 007c14fba6000000, mv, gpr0, hid4
+> 007c16faa6000000, mv, hid5, gpr0
+> 007c16fba6000000, mv, gpr0, hid5
+> 007c1152a6000000, mv, hmeer, gpr0
+> 007c1153a6000000, mv, gpr0, hmeer
+> 007c1052a6000000, mv, hmer, gpr0
+> 007c1053a6000000, mv, gpr0, hmer
+> 007c1852a6000000, mv, hpmc1, gpr0
+> 007c1853a6000000, mv, gpr0, hpmc1
+> 007c1952a6000000, mv, hpmc2, gpr0
+> 007c1953a6000000, mv, gpr0, hpmc2
+> 007c1a52a6000000, mv, hpmc3, gpr0
+> 007c1a53a6000000, mv, gpr0, hpmc3
+> 007c1b52a6000000, mv, hpmc4, gpr0
+> 007c1b53a6000000, mv, gpr0, hpmc4
+> 007c104aa6000000, mv, hsprg0, gpr0
+> 007c104ba6000000, mv, gpr0, hsprg0
+> 007c114aa6000000, mv, hsprg1, gpr0
+> 007c114ba6000000, mv, gpr0, hsprg1
+> 007c1a4aa6000000, mv, hsrr0, gpr0
+> 007c1a4ba6000000, mv, gpr0, hsrr0
+> 007c1b4aa6000000, mv, hsrr1, gpr0
+> 007c1b4ba6000000, mv, gpr0, hsrr1
+> 007c12f2a6000000, mv, icidr0, gpr0
+> 007c12f3a6000000, mv, gpr0, icidr0
+> 007c15f2a6000000, mv, icidr1, gpr0
+> 007c15f3a6000000, mv, gpr0, icidr1
+> 007c11f2a6000000, mv, irmr0, gpr0
+> 007c11f3a6000000, mv, gpr0, irmr0
+> 007c14f2a6000000, mv, irmr1, gpr0
+> 007c14f3a6000000, mv, gpr0, irmr1
+> 007c10f2a6000000, mv, irsr0, gpr0
+> 007c10f3a6000000, mv, gpr0, irsr0
+> 007c13f2a6000000, mv, irsr1, gpr0
+> 007c13f3a6000000, mv, gpr0, irsr1
+> 007c1e4aa6000000, mv, lpcr, gpr0
+> 007c1e4ba6000000, mv, gpr0, lpcr
+> 007c1f4aa6000000, mv, lpidr, gpr0
+> 007c1f4ba6000000, mv, gpr0, lpidr
+> 007c0802a6000000, mv, lr, gpr0
+> 007c0803a6000000, mv, gpr0, lr
+> 007c1bc2a6000000, mv, mmcr0, gpr0
+> 007c1bc3a6000000, mv, gpr0, mmcr0
+> 007c1ec2a6000000, mv, mmcr1, gpr0
+> 007c1ec3a6000000, mv, gpr0, mmcr1
+> 007c12c2a6000000, mv, mmcra, gpr0
+> 007c12c3a6000000, mv, gpr0, mmcra
+> 007c1c4aa6000000, mv, mmcrh, gpr0
+> 007c1c4ba6000000, mv, gpr0, mmcrh
+> 007c0000a6000000, mv, msr, gpr0
+245,318c249,322
+< 0F80002480000000, mv, gpr0, msr
+< 0F824A54C0000000, mv, pcr, gpr0
+< 0F824A74C0000000, mv, gpr0, pcr
+< 0F820154C0000000, mv, pid, gpr0
+< 0F820174C0000000, mv, gpr0, pid
+< 0F83FF54C0000000, mv, pir, gpr0 #Read Only Reg
+< 0F827854C0000000, mv, pmc1, gpr0
+< 0F827874C0000000, mv, gpr0, pmc1
+< 0F829854C0000000, mv, pmc2, gpr0
+< 0F829874C0000000, mv, gpr0, pmc2
+< 0F82B854C0000000, mv, pmc3, gpr0
+< 0F82B874C0000000, mv, gpr0, pmc3
+< 0F82D854C0000000, mv, pmc4, gpr0
+< 0F82D874C0000000, mv, gpr0, pmc4
+< 0F82F854C0000000, mv, pmc5, gpr0
+< 0F82F874C0000000, mv, gpr0, pmc5
+< 0F831854C0000000, mv, pmc6, gpr0
+< 0F831874C0000000, mv, gpr0, pmc6 #PMC7,PMC8 not supported in P7
+< 0F829B54C0000000, mv, pmcr, gpr0
+< 0F829B74C0000000, mv, gpr0, pmcr
+< 0F801C54C0000000, mv, ppr, gpr0  #PPR=TSR - @04
+< 0F801C74C0000000, mv, gpr0, ppr
+< 0F82BB54C0000000, mv, rwmr, gpr0
+< 0F82BB74C0000000, mv, gpr0, rwmr
+< 0F83B854C0000000, mv, sdar, gpr0
+< 0F83B874C0000000, mv, gpr0, sdar
+< 0F832054C0000000, mv, sdr1, gpr0
+< 0F832074C0000000, mv, gpr0, sdr1
+< 0F839854C0000000, mv, siar, gpr0
+< 0F839874C0000000, mv, gpr0, siar
+< 0F820854C0000000, mv, sprg0, gpr0
+< 0F820874C0000000, mv, gpr0, sprg0
+< 0F822854C0000000, mv, sprg1, gpr0
+< 0F822874C0000000, mv, gpr0, sprg1
+< 0F824854C0000000, mv, sprg2, gpr0
+< 0F824874C0000000, mv, gpr0, sprg2
+< 0F826854C0000000, mv, sprg3, gpr0
+< 0F826874C0000000, mv, gpr0, sprg3
+< 0F828954C0000000, mv, spurr, gpr0
+< 0F828974C0000000, mv, gpr0, spurr
+< 0F834054C0000000, mv, srr0, gpr0
+< 0F834074C0000000, mv, gpr0, srr0
+< 0F836054C0000000, mv, srr1, gpr0
+< 0F836074C0000000, mv, gpr0, srr1
+< 0F818854C0000000, mv, tb, gpr0
+< 0F818874C0000000, mv, gpr0, tb
+< 0F838854C0000000, mv, tbl, gpr0
+< 0F838874C0000000, mv, gpr0, tbl
+< 0F83A854C0000000, mv, tbu, gpr0
+< 0F83A874C0000000, mv, gpr0, tbu
+< 0F83A954C0000000, mv, tfmr, gpr0
+< 0F83A974C0000000, mv, gpr0, tfmr
+< f828a54c0000000, mv, tlbindexr, gpr0
+< f828a74c0000000, mv, gpr0, tlbindexr
+< f82ea54c0000000, mv, tlblpidr, gpr0
+< f82ea74c0000000, mv, gpr0, tlblpidr
+< f82fd54c0000000, mv, tlbrmt, gpr0
+< f82fd74c0000000, mv, gpr0, tlbrmt
+< f82ca54c0000000, mv, tlbrpnr, gpr0 #@05
+< f82ca74c0000000, mv, gpr0, tlbrpnr #@05
+< f82aa54c0000000, mv, tlbvpnr, gpr0
+< f82aa74c0000000, mv, gpr0, tlbvpnr
+< 0F821B54C0000000, mv, trig0, gpr0
+< 0F821B74C0000000, mv, gpr0, trig0   #@04
+< 0F823B54C0000000, mv, trig1, gpr0
+< 0F823B74C0000000, mv, gpr0, trig1   #@04
+< 0F825B54C0000000, mv, trig2, gpr0
+< 0F825B74C0000000, mv, gpr0, trig2   #@04
+< 0F833C54C0000000, mv, tscr, gpr0
+< 0F833C74C0000000, mv, gpr0, tscr
+< 0F83A454C0000000, mv, uamor, gpr0
+< 0F83A474C0000000, mv, gpr0, uamor
+< 0F800854C0000000, mv, vrsave, gpr0
+< 0F800874C0000000, mv, gpr0, vrsave
+---
+> 007c000124000000, mv, gpr0, msr
+> 007c1252a6000000, mv, pcr, gpr0
+> 007c1253a6000000, mv, gpr0, pcr
+> 007c100aa6000000, mv, pid, gpr0
+> 007c100ba6000000, mv, gpr0, pid
+> 007c1ffaa6000000, mv, pir, gpr0 #Read Only Reg
+> 007c13c2a6000000, mv, pmc1, gpr0
+> 007c13c3a6000000, mv, gpr0, pmc1
+> 007c14c2a6000000, mv, pmc2, gpr0
+> 007c14c3a6000000, mv, gpr0, pmc2
+> 007c15c2a6000000, mv, pmc3, gpr0
+> 007c15c3a6000000, mv, gpr0, pmc3
+> 007c16c2a6000000, mv, pmc4, gpr0
+> 007c16c3a6000000, mv, gpr0, pmc4
+> 007c17c2a6000000, mv, pmc5, gpr0
+> 007c17c3a6000000, mv, gpr0, pmc5
+> 007c18c2a6000000, mv, pmc6, gpr0
+> 007c18c3a6000000, mv, gpr0, pmc6 #PMC7,PMC8 not supported in P7
+> 007c14daa6000000, mv, pmcr, gpr0
+> 007c14dba6000000, mv, gpr0, pmcr
+> 007c00e2a6000000, mv, ppr, gpr0  #PPR=TSR - @04
+> 007c00e3a6000000, mv, gpr0, ppr
+> 007c15daa6000000, mv, rwmr, gpr0
+> 007c15dba6000000, mv, gpr0, rwmr
+> 007c1dc2a6000000, mv, sdar, gpr0
+> 007c1dc3a6000000, mv, gpr0, sdar
+> 007c1902a6000000, mv, sdr1, gpr0
+> 007c1903a6000000, mv, gpr0, sdr1
+> 007c1cc2a6000000, mv, siar, gpr0
+> 007c1cc3a6000000, mv, gpr0, siar
+> 007c1042a6000000, mv, sprg0, gpr0
+> 007c1043a6000000, mv, gpr0, sprg0
+> 007c1142a6000000, mv, sprg1, gpr0
+> 007c1143a6000000, mv, gpr0, sprg1
+> 007c1242a6000000, mv, sprg2, gpr0
+> 007c1243a6000000, mv, gpr0, sprg2
+> 007c1342a6000000, mv, sprg3, gpr0
+> 007c1343a6000000, mv, gpr0, sprg3
+> 007c144aa6000000, mv, spurr, gpr0
+> 007c144ba6000000, mv, gpr0, spurr
+> 007c1a02a6000000, mv, srr0, gpr0
+> 007c1a03a6000000, mv, gpr0, srr0
+> 007c1b02a6000000, mv, srr1, gpr0
+> 007c1b03a6000000, mv, gpr0, srr1
+> 007c0c42a6000000, mv, tb, gpr0
+> 007c0c43a6000000, mv, gpr0, tb
+> 007c1c42a6000000, mv, tbl, gpr0
+> 007c1c43a6000000, mv, gpr0, tbl
+> 007c1d42a6000000, mv, tbu, gpr0
+> 007c1d43a6000000, mv, gpr0, tbu
+> 007c1d4aa6000000, mv, tfmr, gpr0
+> 007c1d4ba6000000, mv, gpr0, tfmr
+> 007c1452a6000000, mv, tlbindexr, gpr0
+> 007c1453a6000000, mv, gpr0, tlbindexr
+> 007c1752a6000000, mv, tlblpidr, gpr0
+> 007c1753a6000000, mv, gpr0, tlblpidr
+> 007c17eaa6000000, mv, tlbrmt, gpr0
+> 007c17eba6000000, mv, gpr0, tlbrmt
+> 007c1652a6000000, mv, tlbrpnr, gpr0 #@05
+> 007c1653a6000000, mv, gpr0, tlbrpnr #@05
+> 007c1552a6000000, mv, tlbvpnr, gpr0
+> 007c1553a6000000, mv, gpr0, tlbvpnr
+> 007c10daa6000000, mv, trig0, gpr0
+> 007c10dba6000000, mv, gpr0, trig0   #@04
+> 007c11daa6000000, mv, trig1, gpr0
+> 007c11dba6000000, mv, gpr0, trig1   #@04
+> 007c12daa6000000, mv, trig2, gpr0
+> 007c12dba6000000, mv, gpr0, trig2   #@04
+> 007c19e2a6000000, mv, tscr, gpr0
+> 007c19e3a6000000, mv, gpr0, tscr
+> 007c1d22a6000000, mv, uamor, gpr0
+> 007c1d23a6000000, mv, gpr0, uamor
+> 007c0042a6000000, mv, vrsave, gpr0
+> 007c0043a6000000, mv, gpr0, vrsave
+350,413c354,417
+< 0F82A854C0000000, mv, scratch, gpr0  #mfSCOMD 0
+< 0F82A874C0000000, mv, gpr0, scratch  #mtSCOMD 0
+< 0F86A854C0000000, mv, scratch, gpr1
+< 0F86A874C0000000, mv, gpr1, scratch
+< 0F8AA854C0000000, mv, scratch, gpr2
+< 0F8AA874C0000000, mv, gpr2, scratch
+< 0F8EA854C0000000, mv, scratch, gpr3
+< 0F8EA874C0000000, mv, gpr3, scratch
+< 0F92A854C0000000, mv, scratch, gpr4
+< 0F92A874C0000000, mv, gpr4, scratch
+< 0F96A854C0000000, mv, scratch, gpr5
+< 0F96A874C0000000, mv, gpr5, scratch
+< 0F9AA854C0000000, mv, scratch, gpr6
+< 0F9AA874C0000000, mv, gpr6, scratch
+< 0F9EA854C0000000, mv, scratch, gpr7
+< 0F9EA874C0000000, mv, gpr7, scratch
+< 0FA2A854C0000000, mv, scratch, gpr8
+< 0FA2A874C0000000, mv, gpr8, scratch
+< 0FA6A854C0000000, mv, scratch, gpr9
+< 0FA6A874C0000000, mv, gpr9, scratch
+< 0FAAA854C0000000, mv, scratch, gpr10
+< 0FAAA874C0000000, mv, gpr10, scratch
+< 0FAEA854C0000000, mv, scratch, gpr11
+< 0FAEA874C0000000, mv, gpr11, scratch
+< 0FB2A854C0000000, mv, scratch, gpr12
+< 0FB2A874C0000000, mv, gpr12, scratch
+< 0FB6A854C0000000, mv, scratch, gpr13
+< 0FB6A874C0000000, mv, gpr13, scratch
+< 0FBAA854C0000000, mv, scratch, gpr14
+< 0FBAA874C0000000, mv, gpr14, scratch
+< 0FBEA854C0000000, mv, scratch, gpr15
+< 0FBEA874C0000000, mv, gpr15, scratch
+< 0FC2A854C0000000, mv, scratch, gpr16
+< 0FC2A874C0000000, mv, gpr16, scratch
+< 0FC6A854C0000000, mv, scratch, gpr17
+< 0FC6A874C0000000, mv, gpr17, scratch
+< 0FCAA854C0000000, mv, scratch, gpr18
+< 0FCAA874C0000000, mv, gpr18, scratch
+< 0FCEA854C0000000, mv, scratch, gpr19
+< 0FCEA874C0000000, mv, gpr19, scratch
+< 0FD2A854C0000000, mv, scratch, gpr20
+< 0FD2A874C0000000, mv, gpr20, scratch
+< 0FD6A854C0000000, mv, scratch, gpr21
+< 0FD6A874C0000000, mv, gpr21, scratch
+< 0FDAA854C0000000, mv, scratch, gpr22
+< 0FDAA874C0000000, mv, gpr22, scratch
+< 0FDEA854C0000000, mv, scratch, gpr23
+< 0FDEA874C0000000, mv, gpr23, scratch
+< 0FE2A854C0000000, mv, scratch, gpr24
+< 0FE2A874C0000000, mv, gpr24, scratch
+< 0FE6A854C0000000, mv, scratch, gpr25
+< 0FE6A874C0000000, mv, gpr25, scratch
+< 0FEAA854C0000000, mv, scratch, gpr26
+< 0FEAA874C0000000, mv, gpr26, scratch
+< 0FEEA854C0000000, mv, scratch, gpr27
+< 0FEEA874C0000000, mv, gpr27, scratch
+< 0FF2A854C0000000, mv, scratch, gpr28
+< 0FF2A874C0000000, mv, gpr28, scratch
+< 0FF6A854C0000000, mv, scratch, gpr29
+< 0FF6A874C0000000, mv, gpr29, scratch
+< 0FFAA854C0000000, mv, scratch, gpr30
+< 0FFAA874C0000000, mv, gpr30, scratch
+< 0FFEA854C0000000, mv, scratch, gpr31
+< 0FFEA874C0000000, mv, gpr31, scratch
+---
+> 007c1542a6000000, mv, scratch, gpr0  #mfSCOMD 0
+> 007c1543a6000000, mv, gpr0, scratch  #mtSCOMD 0
+> 007c3542a6000000, mv, scratch, gpr1
+> 007c3543a6000000, mv, gpr1, scratch
+> 007c5542a6000000, mv, scratch, gpr2
+> 007c5543a6000000, mv, gpr2, scratch
+> 007c7542a6000000, mv, scratch, gpr3
+> 007c7543a6000000, mv, gpr3, scratch
+> 007c9542a6000000, mv, scratch, gpr4
+> 007c9543a6000000, mv, gpr4, scratch
+> 007cb542a6000000, mv, scratch, gpr5
+> 007cb543a6000000, mv, gpr5, scratch
+> 007cd542a6000000, mv, scratch, gpr6
+> 007cd543a6000000, mv, gpr6, scratch
+> 007cf542a6000000, mv, scratch, gpr7
+> 007cf543a6000000, mv, gpr7, scratch
+> 007d1542a6000000, mv, scratch, gpr8
+> 007d1543a6000000, mv, gpr8, scratch
+> 007d3542a6000000, mv, scratch, gpr9
+> 007d3543a6000000, mv, gpr9, scratch
+> 007d5542a6000000, mv, scratch, gpr10
+> 007d5543a6000000, mv, gpr10, scratch
+> 007d7542a6000000, mv, scratch, gpr11
+> 007d7543a6000000, mv, gpr11, scratch
+> 007d9542a6000000, mv, scratch, gpr12
+> 007d9543a6000000, mv, gpr12, scratch
+> 007db542a6000000, mv, scratch, gpr13
+> 007db543a6000000, mv, gpr13, scratch
+> 007dd542a6000000, mv, scratch, gpr14
+> 007dd543a6000000, mv, gpr14, scratch
+> 007df542a6000000, mv, scratch, gpr15
+> 007df543a6000000, mv, gpr15, scratch
+> 007e1542a6000000, mv, scratch, gpr16
+> 007e1543a6000000, mv, gpr16, scratch
+> 007e3542a6000000, mv, scratch, gpr17
+> 007e3543a6000000, mv, gpr17, scratch
+> 007e5542a6000000, mv, scratch, gpr18
+> 007e5543a6000000, mv, gpr18, scratch
+> 007e7542a6000000, mv, scratch, gpr19
+> 007e7543a6000000, mv, gpr19, scratch
+> 007e9542a6000000, mv, scratch, gpr20
+> 007e9543a6000000, mv, gpr20, scratch
+> 007eb542a6000000, mv, scratch, gpr21
+> 007eb543a6000000, mv, gpr21, scratch
+> 007ed542a6000000, mv, scratch, gpr22
+> 007ed543a6000000, mv, gpr22, scratch
+> 007ef542a6000000, mv, scratch, gpr23
+> 007ef543a6000000, mv, gpr23, scratch
+> 007f1542a6000000, mv, scratch, gpr24
+> 007f1543a6000000, mv, gpr24, scratch
+> 007f3542a6000000, mv, scratch, gpr25
+> 007f3543a6000000, mv, gpr25, scratch
+> 007f5542a6000000, mv, scratch, gpr26
+> 007f5543a6000000, mv, gpr26, scratch
+> 007f7542a6000000, mv, scratch, gpr27
+> 007f7543a6000000, mv, gpr27, scratch
+> 007f9542a6000000, mv, scratch, gpr28
+> 007f9543a6000000, mv, gpr28, scratch
+> 007fb542a6000000, mv, scratch, gpr29
+> 007fb543a6000000, mv, gpr29, scratch
+> 007fd542a6000000, mv, scratch, gpr30
+> 007fd543a6000000, mv, gpr30, scratch
+> 007ff542a6000000, mv, scratch, gpr31
+> 007ff543a6000000, mv, gpr31, scratch
+421,484c425,488
+< 0F80002CC0000000, mv, gpr0, fpr0  #LFD 0 1
+< 0F80000CC0000000, mv, fpr0, gpr0  #STFD 0 1
+< 0F84002CC0000000, mv, gpr0, fpr1
+< 0F84000CC0000000, mv, fpr1, gpr0
+< 0F88002CC0000000, mv, gpr0, fpr2
+< 0F88000CC0000000, mv, fpr2, gpr0
+< 0F8C002CC0000000, mv, gpr0, fpr3
+< 0F8C000CC0000000, mv, fpr3, gpr0
+< 0F90002CC0000000, mv, gpr0, fpr4
+< 0F90000CC0000000, mv, fpr4, gpr0
+< 0F94002CC0000000, mv, gpr0, fpr5
+< 0F94000CC0000000, mv, fpr5, gpr0
+< 0F98002CC0000000, mv, gpr0, fpr6
+< 0F98000CC0000000, mv, fpr6, gpr0
+< 0F9C002CC0000000, mv, gpr0, fpr7
+< 0F9C000CC0000000, mv, fpr7, gpr0
+< 0FA0002CC0000000, mv, gpr0, fpr8
+< 0FA0000CC0000000, mv, fpr8, gpr0
+< 0FA4002CC0000000, mv, gpr0, fpr9
+< 0FA4000CC0000000, mv, fpr9, gpr0
+< 0FA8002CC0000000, mv, gpr0, fpr10
+< 0FA8000CC0000000, mv, fpr10, gpr0
+< 0FAC002CC0000000, mv, gpr0, fpr11
+< 0FAC000CC0000000, mv, fpr11, gpr0
+< 0FB0002CC0000000, mv, gpr0, fpr12
+< 0FB0000CC0000000, mv, fpr12, gpr0
+< 0FB4002CC0000000, mv, gpr0, fpr13
+< 0FB4000CC0000000, mv, fpr13, gpr0
+< 0FB8002CC0000000, mv, gpr0, fpr14
+< 0FB8000CC0000000, mv, fpr14, gpr0
+< 0FBC002CC0000000, mv, gpr0, fpr15
+< 0FBC000CC0000000, mv, fpr15, gpr0
+< 0FC0002CC0000000, mv, gpr0, fpr16
+< 0FC0000CC0000000, mv, fpr16, gpr0
+< 0FC4002CC0000000, mv, gpr0, fpr17
+< 0FC4000CC0000000, mv, fpr17, gpr0
+< 0FC8002CC0000000, mv, gpr0, fpr18
+< 0FC8000CC0000000, mv, fpr18, gpr0
+< 0FCC002CC0000000, mv, gpr0, fpr19
+< 0FCC000CC0000000, mv, fpr19, gpr0
+< 0FD0002CC0000000, mv, gpr0, fpr20
+< 0FD0000CC0000000, mv, fpr20, gpr0
+< 0FD4002CC0000000, mv, gpr0, fpr21
+< 0FD4000CC0000000, mv, fpr21, gpr0
+< 0FD8002CC0000000, mv, gpr0, fpr22
+< 0FD8000CC0000000, mv, fpr22, gpr0
+< 0FDC002CC0000000, mv, gpr0, fpr23
+< 0FDC000CC0000000, mv, fpr23, gpr0
+< 0FE0002CC0000000, mv, gpr0, fpr24
+< 0FE0000CC0000000, mv, fpr24, gpr0
+< 0FE4002CC0000000, mv, gpr0, fpr25
+< 0FE4000CC0000000, mv, fpr25, gpr0
+< 0FE8002CC0000000, mv, gpr0, fpr26
+< 0FE8000CC0000000, mv, fpr26, gpr0
+< 0FEC002CC0000000, mv, gpr0, fpr27
+< 0FEC000CC0000000, mv, fpr27, gpr0
+< 0FF0002CC0000000, mv, gpr0, fpr28
+< 0FF0000CC0000000, mv, fpr28, gpr0
+< 0FF4002CC0000000, mv, gpr0, fpr29
+< 0FF4000CC0000000, mv, fpr29, gpr0
+< 0FF8002CC0000000, mv, gpr0, fpr30
+< 0FF8000CC0000000, mv, fpr30, gpr0
+< 0FFC002CC0000000, mv, gpr0, fpr31
+< 0FFC000CC0000000, mv, fpr31, gpr0
+---
+> 007c000166000000, mv, gpr0, fpr0  #LFD 0 1
+> 007c000066000000, mv, fpr0, gpr0  #STFD 0 1
+> 007c200166000000, mv, gpr0, fpr1
+> 007c200066000000, mv, fpr1, gpr0
+> 007c400166000000, mv, gpr0, fpr2
+> 007c400066000000, mv, fpr2, gpr0
+> 007c600166000000, mv, gpr0, fpr3
+> 007c600066000000, mv, fpr3, gpr0
+> 007c800166000000, mv, gpr0, fpr4
+> 007c800066000000, mv, fpr4, gpr0
+> 007ca00166000000, mv, gpr0, fpr5
+> 007ca00066000000, mv, fpr5, gpr0
+> 007cc00166000000, mv, gpr0, fpr6
+> 007cc00066000000, mv, fpr6, gpr0
+> 007ce00166000000, mv, gpr0, fpr7
+> 007ce00066000000, mv, fpr7, gpr0
+> 007d000166000000, mv, gpr0, fpr8
+> 007d000066000000, mv, fpr8, gpr0
+> 007d200166000000, mv, gpr0, fpr9
+> 007d200066000000, mv, fpr9, gpr0
+> 007d400166000000, mv, gpr0, fpr10
+> 007d400066000000, mv, fpr10, gpr0
+> 007d600166000000, mv, gpr0, fpr11
+> 007d600066000000, mv, fpr11, gpr0
+> 007d800166000000, mv, gpr0, fpr12
+> 007d800066000000, mv, fpr12, gpr0
+> 007da00166000000, mv, gpr0, fpr13
+> 007da00066000000, mv, fpr13, gpr0
+> 007dc00166000000, mv, gpr0, fpr14
+> 007dc00066000000, mv, fpr14, gpr0
+> 007de00166000000, mv, gpr0, fpr15
+> 007de00066000000, mv, fpr15, gpr0
+> 007e000166000000, mv, gpr0, fpr16
+> 007e000066000000, mv, fpr16, gpr0
+> 007e200166000000, mv, gpr0, fpr17
+> 007e200066000000, mv, fpr17, gpr0
+> 007e400166000000, mv, gpr0, fpr18
+> 007e400066000000, mv, fpr18, gpr0
+> 007e600166000000, mv, gpr0, fpr19
+> 007e600066000000, mv, fpr19, gpr0
+> 007e800166000000, mv, gpr0, fpr20
+> 007e800066000000, mv, fpr20, gpr0
+> 007ea00166000000, mv, gpr0, fpr21
+> 007ea00066000000, mv, fpr21, gpr0
+> 007ec00166000000, mv, gpr0, fpr22
+> 007ec00066000000, mv, fpr22, gpr0
+> 007ee00166000000, mv, gpr0, fpr23
+> 007ee00066000000, mv, fpr23, gpr0
+> 007f000166000000, mv, gpr0, fpr24
+> 007f000066000000, mv, fpr24, gpr0
+> 007f200166000000, mv, gpr0, fpr25
+> 007f200066000000, mv, fpr25, gpr0
+> 007f400166000000, mv, gpr0, fpr26
+> 007f400066000000, mv, fpr26, gpr0
+> 007f600166000000, mv, gpr0, fpr27
+> 007f600066000000, mv, fpr27, gpr0
+> 007f800166000000, mv, gpr0, fpr28
+> 007f800066000000, mv, fpr28, gpr0
+> 007fa00166000000, mv, gpr0, fpr29
+> 007fa00066000000, mv, fpr29, gpr0
+> 007fc00166000000, mv, gpr0, fpr30
+> 007fc00066000000, mv, fpr30, gpr0
+> 007fe00166000000, mv, gpr0, fpr31
+> 007fe00066000000, mv, fpr31, gpr0
diff --git a/sbe/build/citest/etc/patches/patchlist.txt b/sbe/build/citest/etc/patches/patchlist.txt
index 6e932f48..4fd0444a 100644
--- a/sbe/build/citest/etc/patches/patchlist.txt
+++ b/sbe/build/citest/etc/patches/patchlist.txt
@@ -8,3 +8,7 @@
 RTC: 144728
 Files : pervasive.act.patch. Currently SUET does not support FSIMBOX KW. Once
         support is in, remove this patch.
+
+RTC: 128984
+Files: chip.act.patch. Added call for executeInstruction module call.
+       p9.inst.patch. Added P9 specific commands for ramming.
diff --git a/sbe/build/citest/etc/workarounds.postsimsetup b/sbe/build/citest/etc/workarounds.postsimsetup
index 083ec4a7..209a7b3f 100755
--- a/sbe/build/citest/etc/workarounds.postsimsetup
+++ b/sbe/build/citest/etc/workarounds.postsimsetup
@@ -25,3 +25,14 @@ echo "+++ Patching standalone.simics"
 mkdir -p $SANDBOXBASE/obj/ppc/simu/scripts/hbfw
 cp $BACKING_BUILD/obj/ppc/simu/scripts/hbfw/standalone.simics $SANDBOXBASE/obj/ppc/simu/scripts/hbfw
 patch -p0 $SANDBOXBASE/obj/ppc/simu/scripts/hbfw/standalone.simics $SBEROOT/sbe/build/citest/etc/patches/standalone.simics.patch
+
+echo "  +++ Add executeInstruction module call"
+echo "  patch -p0 $SANDBOXBASE/src/simu/data/cec-chip/chip.act $SBEROOT/sbe/build/citest/etc/patches/chip.act.patch"
+patch -p0 $SANDBOXBASE/src/simu/data/cec-chip/chip.act $SBEROOT/sbe/build/citest/etc/patches/chip.act.patch
+
+echo "  +++ Update ramming instructions"
+echo "  cp $BACKING_BUILD/src/simu/data/cec-chip/p9.inst $SANDBOXBASE/src/simu/data/cec-chip/p9.inst"
+echo "  patch -p0 $SANDBOXBASE/src/simu/data/cec-chip/p9.inst $SBEROOT/sbe/build/citest/etc/patches/p9.inst.patch"
+cp $BACKING_BUILD/src/simu/data/cec-chip/p9.inst $SANDBOXBASE/src/simu/data/cec-chip/p9.inst
+patch -p0 $SANDBOXBASE/src/simu/data/cec-chip/p9.inst $SBEROOT/sbe/build/citest/etc/patches/p9.inst.patch
+
diff --git a/sbe/sbefw/sbeFifoMsgUtils.C b/sbe/sbefw/sbeFifoMsgUtils.C
index f926bfdd..a86f1363 100644
--- a/sbe/sbefw/sbeFifoMsgUtils.C
+++ b/sbe/sbefw/sbeFifoMsgUtils.C
@@ -294,3 +294,43 @@ uint32_t sbeDownFifoSignalEot (void)
     #undef SBE_FUNC
 }
 
+
+uint32_t sbeDsSendRespHdr(const sbeRespGenHdr_t &i_hdr,
+                          const sbeResponseFfdc_t &i_ffdc )
+{
+    uint32_t rc = SBE_SEC_OPERATION_SUCCESSFUL;
+    do
+    {
+        uint32_t distance = 1; //initialise by 1 for entry count itself.
+        uint32_t len = sizeof( i_hdr )/sizeof(uint32_t);
+        // sbeDownFifoEnq_mult.
+        rc = sbeDownFifoEnq_mult ( len, ( uint32_t *) &i_hdr);
+        if (rc)
+        {
+            break;
+        }
+        distance += len;
+
+        // If no ffdc , exit;
+        if( i_ffdc.getRc() )
+        {
+            len = sizeof(i_ffdc)/sizeof(uint32_t);
+            rc = sbeDownFifoEnq_mult ( len, ( uint32_t *) &i_ffdc);
+            if (rc)
+            {
+                break;
+            }
+            distance += len;
+        }
+        len = sizeof(distance)/sizeof(uint32_t);
+        //@TODO via RTC 129076.
+        //Need to add FFDC data as well.
+        rc = sbeDownFifoEnq_mult ( len, &distance);
+        if (rc)
+        {
+            break;
+        }
+
+    }while(0);
+    return rc;
+}
diff --git a/sbe/sbefw/sbeFifoMsgUtils.H b/sbe/sbefw/sbeFifoMsgUtils.H
index 83d033c4..d9d460f3 100644
--- a/sbe/sbefw/sbeFifoMsgUtils.H
+++ b/sbe/sbefw/sbeFifoMsgUtils.H
@@ -155,4 +155,15 @@ void sbeBuildMinRespHdr ( uint32_t  *io_pBuf,
   */
 uint32_t sbeDownFifoSignalEot (void);
 
+/**
+ * @brief sbeDsSendRespHdr : Send response header to DS FIFO
+ *           - This also sends the FFDC if exist.
+ *
+ * @param[in]    i_hdr     Response Header
+ * @param[in]    i_ffdc    FFDC object
+  *
+  * @return     Rc from the underlying scom utility
+ */
+uint32_t sbeDsSendRespHdr(const sbeRespGenHdr_t &i_hdr,
+                          const sbeResponseFfdc_t &i_ffdc );
 #endif // __SBEFW_SBEFIFOMSGUTILS_H
diff --git a/sbe/sbefw/sbeSpMsg.H b/sbe/sbefw/sbeSpMsg.H
index 7d8e3fb1..df2730cb 100644
--- a/sbe/sbefw/sbeSpMsg.H
+++ b/sbe/sbefw/sbeSpMsg.H
@@ -144,7 +144,7 @@ typedef struct sbeResponseFfdc
       *
       * @return fapiRc
       */
-    uint32_t getRc()
+    uint32_t getRc() const
     {
         return lowFapiRc;
     }
@@ -475,5 +475,50 @@ typedef struct
         }
     }
 }sbeCntlInstRegMsgHdr_t;
+/**
+  * @brief Reg access message header
+  */
+typedef struct
+{
+    uint32_t reserved:8;
+    uint32_t coreChiplet:8;
+    uint32_t threadNr:4;
+    uint32_t regType:4;
+    uint32_t numRegs:8;
+
+    /**
+      * @brief checks if it is valid request.
+      *
+      * @return true if valid request, false otherwise
+      */
+    bool isValidRequest() const
+    {
+        return (( SBE_REG_ACCESS_FPR >= regType )
+                &&( SBE_MAX_REG_ACCESS_REGS >= numRegs )
+                &&( SMT4_THREAD3 >= threadNr )
+                &&( SMT4_CORE0_ID <= coreChiplet )
+                &&( SMT4_CORE_ID_MAX >= coreChiplet )) ? true:false;
+    }
+}sbeRegAccessMsgHdr_t;
+
+/**
+  * @brief reg scom package
+  */
+typedef struct
+{
+    uint32_t regNr;
+    uint32_t hiData;
+    uint32_t lowData;
+
+    /**
+      * @brief data for a register.
+      *
+      * @return data.
+      */
+    uint64_t getData() const
+    {
+        return (((uint64_t)hiData << 32 ) | lowData );
+    }
+}sbeRegAccessPackage_t;
 
 #endif // __SBEFW_SBESP_MSG_H
diff --git a/sbe/sbefw/sbe_sp_intf.H b/sbe/sbefw/sbe_sp_intf.H
index 7f5fac19..62894b6a 100644
--- a/sbe/sbefw/sbe_sp_intf.H
+++ b/sbe/sbefw/sbe_sp_intf.H
@@ -286,6 +286,10 @@ enum sbeSramAccessMode
     DEBUG_MODE     = 0x2,
     CIRCULAR_MODE  = 0x3,
 };
+/*
+ * Constants for maximum number of register supported in reg access chipop.
+ */
+static const uint32_t SBE_MAX_REG_ACCESS_REGS = 64;
 
 /**
  * @brief Error Mode enum
@@ -330,6 +334,17 @@ enum sbeThreadOps
     THREAD_SRESET_INS      = 0x3,
 };
 
+/**
+ *  @brief enums for Reg access register type
+ *
+ */
+enum sbeRegAccesRegType
+{
+    SBE_REG_ACCESS_GPR  = 0x00,
+    SBE_REG_ACCESS_SPR  = 0x01,
+    SBE_REG_ACCESS_FPR  = 0x02,
+};
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/sbe/sbefw/sbecmdgeneric.C b/sbe/sbefw/sbecmdgeneric.C
index 8fe7b6a2..a1d62aa5 100644
--- a/sbe/sbefw/sbecmdgeneric.C
+++ b/sbe/sbefw/sbecmdgeneric.C
@@ -44,6 +44,9 @@ sbeCapabilityRespMsg::sbeCapabilityRespMsg()
 
     capability[INSTRUCTION_CTRL_CAPABILITY_START_IDX] =
                                 CONTROL_INSTRUCTIONS_SUPPPORTED;
+    capability[REGISTER_CAPABILITY_START_IDX] =
+                                GET_REGISTER_SUPPPORTED |
+                                PUT_REGISTER_SUPPPORTED ;
 }
 // Functions
 //----------------------------------------------------------------------------
diff --git a/sbe/sbefw/sbecmdparser.C b/sbe/sbefw/sbecmdparser.C
index 6769be77..9dc6c094 100644
--- a/sbe/sbefw/sbecmdparser.C
+++ b/sbe/sbefw/sbecmdparser.C
@@ -10,6 +10,7 @@
 #include "sbecmdiplcontrol.H"
 #include "sbecmdgeneric.H"
 #include "sbecmdmemaccess.H"
+#include "sbecmdregaccess.H"
 #include "sbecmdcntrldmt.H"
 #include "sbecmdsram.H"
 #include "sbecmdcntlinst.H"
@@ -114,6 +115,22 @@ static sbeCmdStruct_t g_sbeInstructionCntlCmdArray[] =
      SBE_FENCE_AT_CONTINUOUS_IPL,
     },
 };
+//////////////////////////////////////////////////////////////
+// @brief g_sbeRegAccessCmdArray
+//
+//////////////////////////////////////////////////////////////
+static sbeCmdStruct_t g_sbeRegAccessCmdArray [] =
+{
+    {sbeGetReg,
+     SBE_CMD_GETREG,
+     SBE_FENCE_AT_CONTINUOUS_IPL,
+    },
+
+    {sbePutReg,
+     SBE_CMD_PUTREG,
+     SBE_FENCE_AT_CONTINUOUS_IPL,
+    },
+};
 
 //////////////////////////////////////////////////////////////
 // @brief g_sbeCoreStateControlCmdArray
@@ -170,6 +187,12 @@ uint8_t sbeGetCmdStructAttr (const uint8_t  i_cmdClass,
             *o_ppCmd  = (sbeCmdStruct_t*)g_sbeInstructionCntlCmdArray;
             break;
 
+        case SBE_CMD_CLASS_REGISTER_ACCESS:
+            l_numCmds = sizeof(g_sbeRegAccessCmdArray) /
+                        sizeof(sbeCmdStruct_t);
+            *o_ppCmd  = (sbeCmdStruct_t*)g_sbeRegAccessCmdArray;
+            break;
+
         // PSU Commands
         case SBE_PSU_CMD_CLASS_CORE_STATE:
             l_numCmds = sizeof(g_sbeCoreStateControlCmdArray) /
diff --git a/sbe/sbefw/sbecmdregaccess.C b/sbe/sbefw/sbecmdregaccess.C
new file mode 100644
index 00000000..1b0fbe39
--- /dev/null
+++ b/sbe/sbefw/sbecmdregaccess.C
@@ -0,0 +1,248 @@
+/*
+ * @file: ppe/sbe/sbefw/sbecmdregaccess.C
+ *
+ * @brief This file contains the SBE Reg Access chipOps
+ *
+ */
+
+#include "sbecmdregaccess.H"
+#include "sbefifo.H"
+#include "sbe_sp_intf.H"
+#include "sbetrace.H"
+#include "sbeFifoMsgUtils.H"
+#include "p9_ram_core.H"
+
+using namespace fapi2;
+
+Enum_RegType getRegType( const sbeRegAccessMsgHdr_t &regReq)
+{
+    Enum_RegType type = REG_GPR;
+    switch( regReq.regType )
+    {
+        case SBE_REG_ACCESS_SPR:
+            type = REG_SPR;
+            break;
+
+        case SBE_REG_ACCESS_FPR:
+            type = REG_FPR;
+            break;
+    }
+    return type;
+}
+
+//////////////////////////////////////////////////////
+//////////////////////////////////////////////////////
+uint32_t sbeGetReg(uint8_t *i_pArg)
+{
+    #define SBE_FUNC " sbeGetReg "
+    SBE_ENTER(SBE_FUNC);
+
+    uint32_t rc = SBE_SEC_OPERATION_SUCCESSFUL;
+    sbeRegAccessMsgHdr_t regReqMsg;
+    uint32_t reqData[SBE_MAX_REG_ACCESS_REGS];
+    sbeRespGenHdr_t respHdr;
+    respHdr.init();
+    sbeResponseFfdc_t ffdc;
+    ReturnCode fapiRc;
+
+    do
+    {
+        // Get the reg access header
+        uint32_t len  = sizeof(sbeRegAccessMsgHdr_t)/sizeof(uint32_t);
+        rc = sbeUpFifoDeq_mult (len, (uint32_t *)&regReqMsg, false);
+
+        // If FIFO access failure
+        if (rc != SBE_SEC_OPERATION_SUCCESSFUL)
+        {
+            // Let command processor routine to handle the RC.
+            break;
+        }
+        if( false == regReqMsg.isValidRequest() )
+        {
+            SBE_ERROR(SBE_FUNC" Invalid request. core: 0x%02x threadNr:0x%x"
+                      " regType:0x%01x numRegs:0x%02x", regReqMsg.coreChiplet,
+                      regReqMsg.threadNr, regReqMsg.regType, regReqMsg.numRegs);
+
+            respHdr.setStatus( SBE_PRI_INVALID_DATA,
+                               SBE_SEC_GENERIC_FAILURE_IN_EXECUTION);
+            break;
+        }
+
+        len  = regReqMsg.numRegs;
+        rc = sbeUpFifoDeq_mult (len, reqData, true);
+        if (rc != SBE_SEC_OPERATION_SUCCESSFUL)
+        {
+            break;
+        }
+        uint8_t core = regReqMsg.coreChiplet;
+        RamCore ramCore( plat_getTargetHandleByChipletNumber(core),
+                         regReqMsg.threadNr );
+
+        fapiRc = ramCore.ram_setup();
+        if( fapiRc != FAPI2_RC_SUCCESS )
+        {
+            SBE_ERROR(SBE_FUNC" ram_setup failed. threadNr:0x%x"
+                      "chipletId:0x%02x", regReqMsg.threadNr, core);
+            respHdr.setStatus( SBE_PRI_GENERIC_EXECUTION_FAILURE,
+                               SBE_SEC_GENERIC_FAILURE_IN_EXECUTION);
+            ffdc.setRc(fapiRc);
+            break;
+        }
+
+        fapi2::buffer<uint64_t> data64;
+        uint64_t respData = 0;
+        for( uint32_t regIdx = 0; regIdx < regReqMsg.numRegs; regIdx++ )
+        {
+            fapiRc = ramCore.get_reg( getRegType(regReqMsg), reqData[regIdx],
+                                      &data64, true );
+            if( fapiRc != FAPI2_RC_SUCCESS )
+            {
+                SBE_ERROR(SBE_FUNC" get_reg failed. threadNr:0x%x"
+                              "chipletId:0x%02x, regNr:%u regType:%u ",
+                              regReqMsg.threadNr, core, reqData[regIdx],
+                              regReqMsg.regType);
+                respHdr.setStatus( SBE_PRI_GENERIC_EXECUTION_FAILURE,
+                                   SBE_SEC_GENERIC_FAILURE_IN_EXECUTION);
+                ffdc.setRc(fapiRc);
+                break;
+            }
+            SBE_DEBUG(SBE_FUNC" getting response data");
+            respData = data64;
+            // Now enqueue into the downstream FIFO
+            len = sizeof( respData )/sizeof(uint32_t);
+            rc = sbeDownFifoEnq_mult (len, ( uint32_t *)&respData);
+            if (rc)
+            {
+               break;
+            }
+         }
+         // HWP team does not care about cleanup for failure case.
+         // So call cleaup only for success case.
+         if( ffdc.getRc() )
+         {
+             break;
+         }
+         fapiRc = ramCore.ram_cleanup();
+         if( fapiRc != FAPI2_RC_SUCCESS )
+         {
+             SBE_ERROR(SBE_FUNC" ram_cleanup failed. threadNr:0x%x"
+                       "chipletId:0x%02x", regReqMsg.threadNr, core);
+             respHdr.setStatus( SBE_PRI_GENERIC_EXECUTION_FAILURE,
+                               SBE_SEC_GENERIC_FAILURE_IN_EXECUTION);
+             ffdc.setRc(fapiRc);
+         }
+    }while(false);
+
+    if ( SBE_SEC_OPERATION_SUCCESSFUL == rc )
+    {
+        rc = sbeDsSendRespHdr( respHdr, ffdc);
+    }
+
+    return rc;
+    #undef SBE_FUNC
+}
+//////////////////////////////////////////////////////
+//////////////////////////////////////////////////////
+uint32_t sbePutReg(uint8_t *i_pArg)
+{
+    #define SBE_FUNC " sbePutReg "
+    SBE_ENTER(SBE_FUNC);
+
+    uint32_t rc = SBE_SEC_OPERATION_SUCCESSFUL;
+    sbeRegAccessMsgHdr_t regReqMsg;
+    sbeRespGenHdr_t respHdr;
+    respHdr.init();
+    sbeResponseFfdc_t ffdc;
+    ReturnCode fapiRc;
+
+    do
+    {
+        // Get the reg access header
+        uint32_t len  = sizeof(sbeRegAccessMsgHdr_t)/sizeof(uint32_t);
+        rc = sbeUpFifoDeq_mult (len, (uint32_t *)&regReqMsg, false);
+
+        // If FIFO access failure
+        if (rc != SBE_SEC_OPERATION_SUCCESSFUL)
+        {
+            // Let command processor routine to handle the RC.
+            break;
+        }
+        if( false == regReqMsg.isValidRequest() )
+        {
+            SBE_ERROR(SBE_FUNC" Invalid request. threadNr:0x%x"
+                      " regType:0x%02x numRegs:0x%02x", regReqMsg.threadNr,
+                      regReqMsg.regType, regReqMsg.numRegs);
+            respHdr.setStatus( SBE_PRI_INVALID_DATA,
+                               SBE_SEC_GENERIC_FAILURE_IN_EXECUTION);
+            break;
+        }
+
+        sbeRegAccessPackage_t regPkg[SBE_MAX_REG_ACCESS_REGS];
+        len  = (sizeof(sbeRegAccessPackage_t)/sizeof(uint32_t)) * 
+                                                    regReqMsg.numRegs;
+        rc = sbeUpFifoDeq_mult (len, (uint32_t *) regPkg,true );
+        if (rc != SBE_SEC_OPERATION_SUCCESSFUL)
+        {
+            break;
+        }
+        uint8_t core = regReqMsg.coreChiplet;
+        RamCore ramCore( plat_getTargetHandleByChipletNumber(core),
+                         regReqMsg.threadNr );
+
+        fapiRc = ramCore.ram_setup();
+        if( fapiRc != FAPI2_RC_SUCCESS )
+        {
+            SBE_ERROR(SBE_FUNC" ram_setup failed. threadNr:0x%x"
+                      "chipletId:0x%02x", regReqMsg.threadNr, core);
+            respHdr.setStatus( SBE_PRI_GENERIC_EXECUTION_FAILURE,
+                               SBE_SEC_GENERIC_FAILURE_IN_EXECUTION);
+            ffdc.setRc(fapiRc);
+            break;
+        }
+
+        fapi2::buffer<uint64_t> data64;
+        for( uint32_t regIdx = 0; regIdx < regReqMsg.numRegs; regIdx++ )
+        {
+            data64 = regPkg[regIdx].getData();
+            fapiRc = ramCore.put_reg( getRegType(regReqMsg),
+                                      regPkg[regIdx].regNr,
+                                      &data64, true );
+            if( fapiRc != FAPI2_RC_SUCCESS )
+            {
+                SBE_ERROR(SBE_FUNC" get_reg failed. threadNr:0x%x"
+                              "chipletId:0x%02x, regNr:%u regType:%u ",
+                              regReqMsg.threadNr, core, regPkg[regIdx].regNr,
+                              regReqMsg.regType);
+                respHdr.setStatus( SBE_PRI_GENERIC_EXECUTION_FAILURE,
+                                   SBE_SEC_GENERIC_FAILURE_IN_EXECUTION);
+                ffdc.setRc(fapiRc);
+                break;
+            }
+         }
+         // HWP team does not care about cleanup for failure case.
+         // So call cleaup only for success case.
+         if( ffdc.getRc() )
+         {
+             break;
+         }
+         fapiRc = ramCore.ram_cleanup();
+         if( fapiRc )
+         {
+             SBE_ERROR(SBE_FUNC" ram_cleanup failed. threadNr:0x%x"
+                       " chipletId:0x%02x", regReqMsg.threadNr, core);
+             respHdr.setStatus( SBE_PRI_GENERIC_EXECUTION_FAILURE,
+                                SBE_SEC_GENERIC_FAILURE_IN_EXECUTION);
+             ffdc.setRc(fapiRc);
+         }
+
+    }while(false);
+
+    if ( SBE_SEC_OPERATION_SUCCESSFUL == rc )
+    {
+        rc = sbeDsSendRespHdr( respHdr, ffdc);
+    }
+
+    return rc;
+    #undef SBE_FUNC
+}
+
diff --git a/sbe/sbefw/sbecmdregaccess.H b/sbe/sbefw/sbecmdregaccess.H
new file mode 100644
index 00000000..b297fc59
--- /dev/null
+++ b/sbe/sbefw/sbecmdregaccess.H
@@ -0,0 +1,33 @@
+/*
+ * @file: ppe/sbe/sbefw/sbecmdregaccess.H
+ *
+ * @brief This file contains the Interfaces for the SCOM Access chip-ops
+ *
+ */
+
+#ifndef __SBEFW_SBECMDREGACCESS_H
+#define __SBEFW_SBECMDREGACCESS_H
+
+#include <stdint.h>
+
+/**
+  * @brief sbeGetRegs : Get the reg data
+  *
+  * @param[in] i_pArg Buffer to be passed to the function (not used as of now)
+  *
+  * @return    Rc from the FIFO access utility
+  */
+uint32_t sbeGetReg(uint8_t *i_pArg);
+
+
+/**
+  * @brief sbePutRegs : Put the reg data
+  *
+  * @param[in] i_pArg Buffer to be passed to the function (not used as of now)
+  *
+  * @return    Rc from the FIFO access utility
+  */
+uint32_t sbePutReg(uint8_t *i_pArg);
+
+
+#endif /* __SBEFW_SBECMDREGACCESS_H */
diff --git a/sbe/sbefw/sbefwfiles.mk b/sbe/sbefw/sbefwfiles.mk
index f666bdb6..d38df07d 100644
--- a/sbe/sbefw/sbefwfiles.mk
+++ b/sbe/sbefw/sbefwfiles.mk
@@ -14,6 +14,8 @@ SBEFW-CPP-SOURCES += sbecmdcntrldmt.C
 SBEFW-CPP-SOURCES += sbecmdsram.C
 SBEFW-CPP-SOURCES += sberegaccess.C
 SBEFW-CPP-SOURCES += sbecmdcntlinst.C
+SBEFW-CPP-SOURCES += sbecmdregaccess.C
+
 SBEFW-C-SOURCES =
 SBEFW-S-SOURCES =
 
diff --git a/sbe/test/test.xml b/sbe/test/test.xml
index 6fb16651..07d1f1a0 100755
--- a/sbe/test/test.xml
+++ b/sbe/test/test.xml
@@ -10,6 +10,7 @@
           <include>../simics/targets/p9_nimbus/sbeTest/testPutGetMem.xml</include>
           <include>../simics/targets/p9_nimbus/sbeTest/testSram.xml</include>
           <include>../simics/targets/p9_nimbus/sbeTest/testCntlInstruction.xml</include>
+          <include>../simics/targets/p9_nimbus/sbeTest/testRegAccess.xml</include>
           <testcase>
               <simcmd>sbe-trace 0</simcmd>
           </testcase>
diff --git a/sbe/test/testGetCapabilities.py b/sbe/test/testGetCapabilities.py
index 4fb13a7f..f9292532 100755
--- a/sbe/test/testGetCapabilities.py
+++ b/sbe/test/testGetCapabilities.py
@@ -17,7 +17,7 @@ EXPDATA1 = [0x0,0x0,0x0,0x0,
 
 EXPDATA2 = [0xa4,0x0,0x0,0x0f, #GetMemPba/PutMemPba/GetSramOcc/PutSramOcc
            0x0,0x0,0x0,0x0,
-           0x0,0x0,0x0,0x0,
+           0xa5,0x0,0x0,0x03, #GetReg/PutReg
            0x0,0x0,0x0,0x0,
            0x0,0x0,0x0,0x0,
            0x0,0x0,0x0,0x0,
diff --git a/sbe/test/testPutGetRegFpr.py b/sbe/test/testPutGetRegFpr.py
new file mode 100755
index 00000000..63cf4186
--- /dev/null
+++ b/sbe/test/testPutGetRegFpr.py
@@ -0,0 +1,58 @@
+import sys
+sys.path.append("targets/p9_nimbus/sbeTest" )
+import testUtil
+err = False
+
+PUTREG_TESTDATA =  [0,0,0,9,
+                    0,0,0xA5,0x02,
+                    0x00,0x20,0x02,0x02, # two fpr registers
+                    0,0,0x0,0x01,
+                    0,0,0x0,0x0,
+                    0,0,0x0,0x1,
+                    0,0,0x0,0x02,
+                    0,0,0x0,0x0,
+                    0,0,0x0,0x2 ]
+
+PUTREG_EXPDATA =  [0xc0,0xde,0xa5,0x02,
+                   0x0,0x0,0x0,0x0,
+                   0x00,0x0,0x0,0x03];
+
+GETREG_TESTDATA = [0,0,0,5,
+                    0,0,0xA5,0x01,
+                    0x00,0x20,0x02,0x02,  #two fpr registers
+                    0,0,0x0,0x01,
+                    0,0,0x0,0x02 ]
+
+GETREG_EXPDATA = [0x00,0x00,0x00,0x00,
+                   0x00,0x00,0x00,0x01,
+                   0x00,0x00,0x00,0x00,
+                   0x00,0x00,0x00,0x02,
+                   0xc0,0xde,0xa5,0x01,
+                   0x0,0x0,0x0,0x0,
+                   0x00,0x0,0x0,0x03];
+
+# MAIN Test Run Starts Here...
+#-------------------------------------------------
+def main( ):
+    testUtil.runCycles( 10000000 )
+    testUtil.writeUsFifo( PUTREG_TESTDATA )
+    testUtil.writeEot( )
+    testUtil.readDsFifo( PUTREG_EXPDATA )
+    testUtil.readEot( )
+    testUtil.writeUsFifo( GETREG_TESTDATA )
+    testUtil.writeEot( )
+    testUtil.readDsFifo( GETREG_EXPDATA )
+    testUtil.readEot( )
+
+#-------------------------------------------------
+# Calling all test code
+#-------------------------------------------------
+main()
+
+if err:
+    print ("\nTest Suite completed with error(s)")
+    #sys.exit(1)
+else:
+    print ("\nTest Suite completed with no errors")
+    #sys.exit(0);
+
diff --git a/sbe/test/testPutGetRegGpr.py b/sbe/test/testPutGetRegGpr.py
new file mode 100755
index 00000000..ce5891e7
--- /dev/null
+++ b/sbe/test/testPutGetRegGpr.py
@@ -0,0 +1,58 @@
+import sys
+sys.path.append("targets/p9_nimbus/sbeTest" )
+import testUtil
+err = False
+
+PUTREG_TESTDATA =  [0,0,0,9,
+                    0,0,0xA5,0x02,
+                    0x00,0x20,0x00,0x02, # two gpr registers
+                    0,0,0x0,0x07,
+                    0,0,0x0,0x0,
+                    0,0,0x0,0x1,
+                    0,0,0x0,0x08,
+                    0,0,0x0,0x0,
+                    0,0,0x0,0x2 ]
+
+PUTREG_EXPDATA =  [0xc0,0xde,0xa5,0x02,
+                   0x0,0x0,0x0,0x0,
+                   0x00,0x0,0x0,0x03];
+
+GETREG_TESTDATA = [0,0,0,5,
+                    0,0,0xA5,0x01,
+                    0x00,0x20,0x00,0x02, # two gpr registers
+                    0,0,0x0,0x07,
+                    0,0,0x0,0x08 ]
+
+GETREG_EXPDATA = [0x00,0x00,0x00,0x00,
+                   0x00,0x00,0x00,0x01,
+                   0x00,0x00,0x00,0x00,
+                   0x00,0x00,0x00,0x02,
+                   0xc0,0xde,0xa5,0x01,
+                   0x0,0x0,0x0,0x0,
+                   0x00,0x0,0x0,0x03];
+
+# MAIN Test Run Starts Here...
+#-------------------------------------------------
+def main( ):
+    testUtil.runCycles( 10000000 )
+    testUtil.writeUsFifo( PUTREG_TESTDATA )
+    testUtil.writeEot( )
+    testUtil.readDsFifo( PUTREG_EXPDATA )
+    testUtil.readEot( )
+    testUtil.writeUsFifo( GETREG_TESTDATA )
+    testUtil.writeEot( )
+    testUtil.readDsFifo( GETREG_EXPDATA )
+    testUtil.readEot( )
+
+#-------------------------------------------------
+# Calling all test code
+#-------------------------------------------------
+main()
+
+if err:
+    print ("\nTest Suite completed with error(s)")
+    #sys.exit(1)
+else:
+    print ("\nTest Suite completed with no errors")
+    #sys.exit(0);
+
diff --git a/sbe/test/testPutGetRegSpr.py b/sbe/test/testPutGetRegSpr.py
new file mode 100755
index 00000000..82f7c8d2
--- /dev/null
+++ b/sbe/test/testPutGetRegSpr.py
@@ -0,0 +1,58 @@
+import sys
+sys.path.append("targets/p9_nimbus/sbeTest" )
+import testUtil
+err = False
+
+PUTREG_TESTDATA =  [0,0,0,9,
+                    0,0,0xA5,0x02,
+                    0x00,0x20,0x01,0x02, # two spr registers
+                    0,0,0x0,0x08,
+                    0,0,0x0,0x0,
+                    0,0,0x0,0x1,
+                    0,0,0x0,0x09,
+                    0,0,0x0,0x0,
+                    0,0,0x0,0x2 ]
+
+PUTREG_EXPDATA =  [0xc0,0xde,0xa5,0x02,
+                   0x0,0x0,0x0,0x0,
+                   0x00,0x0,0x0,0x03];
+
+GETREG_TESTDATA = [0,0,0,5,
+                    0,0,0xA5,0x01,
+                    0x00,0x20,0x01,0x02, # two spr registers
+                    0,0,0x0,0x08,
+                    0,0,0x0,0x09 ]
+
+GETREG_EXPDATA = [0x00,0x00,0x00,0x00,
+                   0x00,0x00,0x00,0x01,
+                   0x00,0x00,0x00,0x00,
+                   0x00,0x00,0x00,0x02,
+                   0xc0,0xde,0xa5,0x01,
+                   0x0,0x0,0x0,0x0,
+                   0x00,0x0,0x0,0x03];
+
+# MAIN Test Run Starts Here...
+#-------------------------------------------------
+def main( ):
+    testUtil.runCycles( 10000000 )
+    testUtil.writeUsFifo( PUTREG_TESTDATA )
+    testUtil.writeEot( )
+    testUtil.readDsFifo( PUTREG_EXPDATA )
+    testUtil.readEot( )
+    testUtil.writeUsFifo( GETREG_TESTDATA )
+    testUtil.writeEot( )
+    testUtil.readDsFifo( GETREG_EXPDATA )
+    testUtil.readEot( )
+
+#-------------------------------------------------
+# Calling all test code
+#-------------------------------------------------
+main()
+
+if err:
+    print ("\nTest Suite completed with error(s)")
+    #sys.exit(1)
+else:
+    print ("\nTest Suite completed with no errors")
+    #sys.exit(0);
+
diff --git a/sbe/test/testRegAccess.xml b/sbe/test/testRegAccess.xml
new file mode 100755
index 00000000..53cfa4c1
--- /dev/null
+++ b/sbe/test/testRegAccess.xml
@@ -0,0 +1,15 @@
+<?xml version="1.0" encoding="UTF-8"?>
+
+      <testcase>
+          <simcmd>run-python-file targets/p9_nimbus/sbeTest/testPutGetRegGpr.py</simcmd>
+          <exitonerror>yes</exitonerror>
+      </testcase>
+      <testcase>
+          <simcmd>run-python-file targets/p9_nimbus/sbeTest/testPutGetRegFpr.py</simcmd>
+          <exitonerror>yes</exitonerror>
+      </testcase>
+      <testcase>
+          <simcmd>run-python-file targets/p9_nimbus/sbeTest/testPutGetRegSpr.py</simcmd>
+          <exitonerror>yes</exitonerror>
+      </testcase>
+