Support for Control Instruction

Change-Id: Ib6f1e15a199f08aeb48e2486f0be901832ff4127
RTC:128325
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/21787
Tested-by: Jenkins Server
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: Santosh S. Puranik <santosh.puranik@in.ibm.com>
Reviewed-by: AMIT J. TENDOLKAR <amit.tendolkar@in.ibm.com>

5 files changed, 470 insertions, 3 deletions

diff --git a/sbe/test/test.xml b/sbe/test/test.xml
index f5fdb966..6fb16651 100755
--- a/sbe/test/test.xml
+++ b/sbe/test/test.xml
@@ -3,14 +3,13 @@
 <integrationtest>
 	<platform startsimargs="--notar --norun --sim_parms -nre">
 		<machine>%%machine%%</machine>
-
         <test>
-           <!-- Set IVPR to point to sbe start address -->
           <include>../simics/targets/p9_nimbus/sbeTest/testIstep.xml</include>
           <include>../simics/targets/p9_nimbus/sbeTest/testScom.xml</include>
           <include>../simics/targets/p9_nimbus/sbeTest/testGeneric.xml</include>
           <include>../simics/targets/p9_nimbus/sbeTest/testPutGetMem.xml</include>
           <include>../simics/targets/p9_nimbus/sbeTest/testSram.xml</include>
+          <include>../simics/targets/p9_nimbus/sbeTest/testCntlInstruction.xml</include>
           <testcase>
               <simcmd>sbe-trace 0</simcmd>
           </testcase>
diff --git a/sbe/test/testCntlInstruction.py b/sbe/test/testCntlInstruction.py
new file mode 100644
index 00000000..df0a9d46
--- /dev/null
+++ b/sbe/test/testCntlInstruction.py
@@ -0,0 +1,453 @@
+import sys
+sys.path.append("targets/p9_nimbus/sbeTest" )
+import testUtil
+err = False
+#from testWrite import *
+
+LOOP_COUNT = 1
+
+#Invalid Input
+INST_INVALID_TESTDATA = [0,0,0,3,
+                         0,0,0xa7,0x01,
+                         0,1,0x20,0xee]
+
+
+INST_INVALID_EXPDATA_ERR = [0xc0,0xde,0xa7,0x01,
+                            0x00,0x02,0x00,0x0A,
+                            0x00,0x00,0x00,0x03]
+
+# STOP Ins
+# core 0 thread 0 STOP WARN FLAG as true
+INST_STOP_0_0_TESTDATA_WITH_WARN_FLG  =  [0,0,0,0x03,
+                                               0,0,0xa7,0x01,
+                                               0,1,0x20,0x01]
+
+# core 0 thread 1 STOP WARN FLAG as true
+INST_STOP_0_1_TESTDATA_WITH_WARN_FLG  =  [0,0,0,0x03,
+                                               0,0,0xa7,0x01,
+                                               0,1,0x20,0x11]
+
+# core 0 thread 2 STOP WARN FLAG as true
+INST_STOP_0_2_TESTDATA_WITH_WARN_FLG  =  [0,0,0,0x03,
+                                               0,0,0xa7,0x01,
+                                               0,1,0x20,0x21]
+
+# core 0 thread 3 STOP with WARN FLAG as true
+INST_STOP_0_3_TESTDATA_WITH_WARN_FLG  =  [0,0,0,0x03,
+                                               0,0,0xa7,0x01,
+                                               0,1,0x20,0x31]
+
+# core 0 thread 0 STOP WARN FLAG as false
+INST_STOP_0_0_TESTDATA_WITHOUT_WARN_FLG  =  [0,0,0,0x03,
+                                               0,0,0xa7,0x01,
+                                               0,0,0x20,0x01]
+
+# core 0 thread 1 STOP WARN FLAG as false
+INST_STOP_0_1_TESTDATA_WITHOUT_WARN_FLG  =  [0,0,0,0x03,
+                                               0,0,0xa7,0x01,
+                                               0,0,0x20,0x11]
+
+# core 0 thread 2 STOP WARN FLAG as false
+INST_STOP_0_2_TESTDATA_WITHOUT_WARN_FLG  =  [0,0,0,0x03,
+                                               0,0,0xa7,0x01,
+                                               0,0,0x20,0x21]
+
+# core 0 thread 3 STOP WARN FLAG as false
+INST_STOP_0_3_TESTDATA_WITHOUT_WARN_FLG  =  [0,0,0,0x03,
+                                               0,0,0xa7,0x01,
+                                               0,0,0x20,0x31]
+
+# Stop All thread in Core0 with warn flag true
+INST_STOP0_ALL_TESTDATA_WITH_WARN_FLG =      [0,0,0,0x03,
+                                              0,0,0xa7,0x01,
+                                              0,1,0x20,0xf1]
+
+# Stop All thread in Core0 with warn flag false
+INST_STOP0_ALL_TESTDATA_WITHOUT_WARN_FLG =      [0,0,0,0x03,
+                                              0,0,0xa7,0x01,
+                                              0,0,0x20,0xf1]
+
+
+# START Ins
+# core 0 thread 0 START WARN FLAG as true
+INST_START_0_0_TESTDATA_WITH_WARN_FLG  =  [0,0,0,0x03,
+                                               0,0,0xa7,0x01,
+                                               0,1,0x20,0x00]
+
+# core 0 thread 1 START WARN FLAG as true
+INST_START_0_1_TESTDATA_WITH_WARN_FLG  =  [0,0,0,0x03,
+                                               0,0,0xa7,0x01,
+                                               0,1,0x20,0x10]
+
+# core 0 thread 2 START WARN FLAG as true
+INST_START_0_2_TESTDATA_WITH_WARN_FLG  =  [0,0,0,0x03,
+                                               0,0,0xa7,0x01,
+                                               0,1,0x20,0x20]
+
+# core 0 thread 3 START with WARN FLAG as true
+INST_START_0_3_TESTDATA_WITH_WARN_FLG  =  [0,0,0,0x03,
+                                               0,0,0xa7,0x01,
+                                               0,1,0x20,0x30]
+
+# core 0 thread 0 START WARN FLAG as false
+INST_START_0_0_TESTDATA_WITHOUT_WARN_FLG  =  [0,0,0,0x03,
+                                               0,0,0xa7,0x01,
+                                               0,0,0x20,0x00]
+
+# core 0 thread 1 START WARN FLAG as false
+INST_START_0_1_TESTDATA_WITHOUT_WARN_FLG  =  [0,0,0,0x03,
+                                               0,0,0xa7,0x01,
+                                               0,0,0x20,0x10]
+
+# core 0 thread 2 START WARN FLAG as false
+INST_START_0_2_TESTDATA_WITHOUT_WARN_FLG  =  [0,0,0,0x03,
+                                               0,0,0xa7,0x01,
+                                               0,0,0x20,0x20]
+
+# core 0 thread 3 START WARN FLAG as false
+INST_START_0_3_TESTDATA_WITHOUT_WARN_FLG  =  [0,0,0,0x03,
+                                               0,0,0xa7,0x01,
+                                               0,0,0x20,0x30]
+
+# Start All thread in Core0 with warn flag true
+INST_START0_ALL_TESTDATA_WITH_WARN_FLG =      [0,0,0,0x03,
+                                              0,0,0xa7,0x01,
+                                              0,1,0x20,0xf0]
+
+# Start All thread in Core0 with warn flag false
+INST_START0_ALL_TESTDATA_WITHOUT_WARN_FLG =      [0,0,0,0x03,
+                                              0,0,0xa7,0x01,
+                                              0,0,0x20,0xf0]
+
+# STEP Ins
+# core 0 thread 0 STEP WARN FLAG as true
+INST_STEP_0_0_TESTDATA_WITH_WARN_FLG  =  [0,0,0,0x03,
+                                          0,0,0xa7,0x01,
+                                          0,1,0x20,0x02]
+
+# core 0 thread 1 STEP WARN FLAG as true
+INST_STEP_0_1_TESTDATA_WITH_WARN_FLG  =  [0,0,0,0x03,
+                                          0,0,0xa7,0x01,
+                                          0,1,0x20,0x12]
+
+# core 0 thread 2 STEP WARN FLAG as true
+INST_STEP_0_2_TESTDATA_WITH_WARN_FLG  =  [0,0,0,0x03,
+                                          0,0,0xa7,0x01,
+                                          0,1,0x20,0x22]
+
+# core 0 thread 3 STEP with WARN FLAG as true
+INST_STEP_0_3_TESTDATA_WITH_WARN_FLG  =  [0,0,0,0x03,
+                                          0,0,0xa7,0x01,
+                                          0,1,0x20,0x32]
+
+# core 0 thread 0 STEP WARN FLAG as false
+INST_STEP_0_0_TESTDATA_WITHOUT_WARN_FLG  =  [0,0,0,0x03,
+                                             0,0,0xa7,0x01,
+                                             0,0,0x20,0x02]
+
+# core 0 thread 1 STEP WARN FLAG as false
+INST_STEP_0_1_TESTDATA_WITHOUT_WARN_FLG  =  [0,0,0,0x03,
+                                             0,0,0xa7,0x01,
+                                             0,0,0x20,0x12]
+
+# core 0 thread 2 STEP WARN FLAG as false
+INST_STEP_0_2_TESTDATA_WITHOUT_WARN_FLG  =  [0,0,0,0x03,
+                                             0,0,0xa7,0x01,
+                                             0,0,0x20,0x22]
+
+# core 0 thread 3 STEP WARN FLAG as false
+INST_STEP_0_3_TESTDATA_WITHOUT_WARN_FLG  =  [0,0,0,0x03,
+                                             0,0,0xa7,0x01,
+                                             0,0,0x20,0x32]
+
+# Step All thread in Core0 with warn flag true
+INST_STEP0_ALL_TESTDATA_WITH_WARN_FLG =      [0,0,0,0x03,
+                                              0,0,0xa7,0x01,
+                                              0,1,0x20,0xf2]
+
+# Step All thread in Core0 with warn flag false
+INST_STEP0_ALL_TESTDATA_WITHOUT_WARN_FLG =   [0,0,0,0x03,
+                                              0,0,0xa7,0x01,
+                                              0,0,0x20,0xf2]
+
+# SRESET Ins
+# core 0 thread 0 SRESET WARN FLAG as true
+INST_SRESET_0_0_TESTDATA_WITH_WARN_FLG  =  [0,0,0,0x03,
+                                          0,0,0xa7,0x01,
+                                          0,1,0x20,0x03]
+
+# core 0 thread 1 SRESET WARN FLAG as true
+INST_SRESET_0_1_TESTDATA_WITH_WARN_FLG  =  [0,0,0,0x03,
+                                          0,0,0xa7,0x01,
+                                          0,1,0x20,0x13]
+
+# core 0 thread 2 SRESET WARN FLAG as true
+INST_SRESET_0_2_TESTDATA_WITH_WARN_FLG  =  [0,0,0,0x03,
+                                          0,0,0xa7,0x01,
+                                          0,1,0x20,0x23]
+
+# core 0 thread 3 SRESET with WARN FLAG as true
+INST_SRESET_0_3_TESTDATA_WITH_WARN_FLG  =  [0,0,0,0x03,
+                                          0,0,0xa7,0x01,
+                                          0,1,0x20,0x33]
+
+# core 0 thread 0 SRESET WARN FLAG as false
+INST_SRESET_0_0_TESTDATA_WITHOUT_WARN_FLG  =  [0,0,0,0x03,
+                                             0,0,0xa7,0x01,
+                                             0,0,0x20,0x03]
+
+# core 0 thread 1 SRESET WARN FLAG as false
+INST_SRESET_0_1_TESTDATA_WITHOUT_WARN_FLG  =  [0,0,0,0x03,
+                                             0,0,0xa7,0x01,
+                                             0,0,0x20,0x13]
+
+# core 0 thread 2 SRESET WARN FLAG as false
+INST_SRESET_0_2_TESTDATA_WITHOUT_WARN_FLG  =  [0,0,0,0x03,
+                                             0,0,0xa7,0x01,
+                                             0,0,0x20,0x23]
+
+# core 0 thread 3 SRESET WARN FLAG as false
+INST_SRESET_0_3_TESTDATA_WITHOUT_WARN_FLG  =  [0,0,0,0x03,
+                                             0,0,0xa7,0x01,
+                                             0,0,0x20,0x33]
+
+# Sreset All thread in Core0 with warn flag true
+INST_SRESET0_ALL_TESTDATA_WITH_WARN_FLG =      [0,0,0,0x03,
+                                              0,0,0xa7,0x01,
+                                              0,1,0x20,0xf3]
+
+# Sreset All thread in Core0 with warn flag false
+INST_SRESET0_ALL_TESTDATA_WITHOUT_WARN_FLG =   [0,0,0,0x03,
+                                              0,0,0xa7,0x01,
+                                              0,0,0x20,0xf3]
+
+
+INST_EXPDATA  =     [0xc0,0xde,0xa7,0x01,
+                     0x0,0x0,0x0,0x0,
+                     0x00,0x0,0x0,0x03]
+
+INST_EXPDATA_ERR = [0xc0,0xde,0xa7,0x01,
+                    0x00,0xFE,0x00,0x0A,
+                    0x00,0x00,0x00,0x03]
+
+STOP_INST_EXPDATA_ERR_WTH_FFDC = [0xc0,0xde,0xa7,0x01,
+                                  0x00,0xFE,0x00,0x0A,
+                                  0xFF,0xDC,0x00,0x03,
+                                  0x00,0x00,0x00,0x00,
+                                  0x00,0xCE,0xBC,0xB2,
+                                  0x00,0x00,0x00,0x06]
+
+START_INST_EXPDATA_ERR_WTH_FFDC = [0xc0,0xde,0xa7,0x01,
+                                  0x00,0xFE,0x00,0x0A,
+                                  0xFF,0xDC,0x00,0x03,
+                                  0x00,0x00,0x00,0x00,
+                                  0x00,0x25,0x64,0xDB,
+                                  0x00,0x00,0x00,0x06]
+
+STEP_INST_EXPDATA_ERR_WTH_FFDC = [0xc0,0xde,0xa7,0x01,
+                                  0x00,0xFE,0x00,0x0A,
+                                  0xFF,0xDC,0x00,0x03,
+                                  0x00,0x00,0x00,0x00,
+                                  0x00,0x0D,0x06,0x8E,
+                                  0x00,0x00,0x00,0x06]
+
+# MAIN Test Run Starts Here...
+#-------------------------------------------------
+def main( ):
+    testUtil.runCycles( 10000000 )
+    #Try an invalid data case
+    testUtil.writeUsFifo( INST_INVALID_TESTDATA )
+    testUtil.writeEot( )
+    testUtil.readDsFifo( INST_INVALID_EXPDATA_ERR )
+    testUtil.readEot( )
+
+    # Control Instruction Message - Stop
+    testUtil.writeUsFifo( INST_STOP_0_0_TESTDATA_WITH_WARN_FLG )
+    testUtil.writeEot( )
+    testUtil.readDsFifo( INST_EXPDATA )
+    testUtil.readEot( )
+    testUtil.writeUsFifo( INST_STOP_0_1_TESTDATA_WITH_WARN_FLG )
+    testUtil.writeEot( )
+    testUtil.readDsFifo( INST_EXPDATA )
+    testUtil.readEot( )
+    testUtil.writeUsFifo( INST_STOP_0_2_TESTDATA_WITH_WARN_FLG )
+    testUtil.writeEot( )
+    testUtil.readDsFifo( INST_EXPDATA )
+    testUtil.readEot( )
+    testUtil.writeUsFifo( INST_STOP_0_3_TESTDATA_WITH_WARN_FLG )
+    testUtil.writeEot( )
+    testUtil.readDsFifo( INST_EXPDATA )
+    testUtil.readEot( )
+    testUtil.writeUsFifo( INST_STOP_0_0_TESTDATA_WITHOUT_WARN_FLG )
+    testUtil.writeEot( )
+    testUtil.readDsFifo( STOP_INST_EXPDATA_ERR_WTH_FFDC )
+    testUtil.readEot( )
+    testUtil.writeUsFifo( INST_STOP_0_1_TESTDATA_WITHOUT_WARN_FLG )
+    testUtil.writeEot( )
+    testUtil.readDsFifo( STOP_INST_EXPDATA_ERR_WTH_FFDC )
+    testUtil.readEot( )
+    testUtil.writeUsFifo( INST_STOP_0_2_TESTDATA_WITHOUT_WARN_FLG )
+    testUtil.writeEot( )
+    testUtil.readDsFifo( STOP_INST_EXPDATA_ERR_WTH_FFDC )
+    testUtil.readEot( )
+    testUtil.writeUsFifo( INST_STOP_0_3_TESTDATA_WITHOUT_WARN_FLG )
+    testUtil.writeEot( )
+    testUtil.readDsFifo( STOP_INST_EXPDATA_ERR_WTH_FFDC )
+    testUtil.readEot( )
+
+    #stop all thread in core0
+    testUtil.writeUsFifo( INST_STOP0_ALL_TESTDATA_WITH_WARN_FLG )
+    testUtil.writeEot( )
+    testUtil.readDsFifo( INST_EXPDATA )
+    testUtil.readEot( )
+    testUtil.writeUsFifo( INST_STOP0_ALL_TESTDATA_WITHOUT_WARN_FLG )
+    testUtil.writeEot( )
+    testUtil.readDsFifo( STOP_INST_EXPDATA_ERR_WTH_FFDC )
+    testUtil.readEot( )
+
+    # Control Instruction Message - Start
+    testUtil.writeUsFifo( INST_START_0_0_TESTDATA_WITH_WARN_FLG )
+    testUtil.writeEot( )
+    testUtil.readDsFifo( INST_EXPDATA )
+    testUtil.readEot( )
+    testUtil.writeUsFifo( INST_START_0_1_TESTDATA_WITH_WARN_FLG )
+    testUtil.writeEot( )
+    testUtil.readDsFifo( INST_EXPDATA )
+    testUtil.readEot( )
+    testUtil.writeUsFifo( INST_START_0_2_TESTDATA_WITH_WARN_FLG )
+    testUtil.writeEot( )
+    testUtil.readDsFifo( INST_EXPDATA )
+    testUtil.readEot( )
+    testUtil.writeUsFifo( INST_START_0_3_TESTDATA_WITH_WARN_FLG )
+    testUtil.writeEot( )
+    testUtil.readDsFifo( INST_EXPDATA )
+    testUtil.readEot( )
+
+    testUtil.writeUsFifo( INST_START_0_0_TESTDATA_WITHOUT_WARN_FLG )
+    testUtil.writeEot( )
+    testUtil.readDsFifo( START_INST_EXPDATA_ERR_WTH_FFDC )
+    testUtil.readEot( )
+    testUtil.writeUsFifo( INST_START_0_1_TESTDATA_WITHOUT_WARN_FLG )
+    testUtil.writeEot( )
+    testUtil.readDsFifo( START_INST_EXPDATA_ERR_WTH_FFDC )
+    testUtil.readEot( )
+    testUtil.writeUsFifo( INST_START_0_2_TESTDATA_WITHOUT_WARN_FLG )
+    testUtil.writeEot( )
+    testUtil.readDsFifo( START_INST_EXPDATA_ERR_WTH_FFDC )
+    testUtil.readEot( )
+    testUtil.writeUsFifo( INST_START_0_3_TESTDATA_WITHOUT_WARN_FLG )
+    testUtil.writeEot( )
+    testUtil.readDsFifo( START_INST_EXPDATA_ERR_WTH_FFDC )
+    testUtil.readEot( )
+
+    #start all thread in core0
+    testUtil.writeUsFifo( INST_START0_ALL_TESTDATA_WITH_WARN_FLG )
+    testUtil.writeEot( )
+    testUtil.readDsFifo( INST_EXPDATA )
+    testUtil.readEot( )
+    testUtil.writeUsFifo( INST_START0_ALL_TESTDATA_WITHOUT_WARN_FLG )
+    testUtil.writeEot( )
+    testUtil.readDsFifo( START_INST_EXPDATA_ERR_WTH_FFDC )
+    testUtil.readEot( )
+
+    # Control Instruction Message - Step
+    testUtil.writeUsFifo( INST_STEP_0_0_TESTDATA_WITH_WARN_FLG )
+    testUtil.writeEot( )
+    testUtil.readDsFifo( INST_EXPDATA )
+    testUtil.readEot( )
+    testUtil.writeUsFifo( INST_STEP_0_1_TESTDATA_WITH_WARN_FLG )
+    testUtil.writeEot( )
+    testUtil.readDsFifo( INST_EXPDATA )
+    testUtil.readEot( )
+    testUtil.writeUsFifo( INST_STEP_0_2_TESTDATA_WITH_WARN_FLG )
+    testUtil.writeEot( )
+    testUtil.readDsFifo( INST_EXPDATA )
+    testUtil.readEot( )
+    testUtil.writeUsFifo( INST_STEP_0_3_TESTDATA_WITH_WARN_FLG )
+    testUtil.writeEot( )
+    testUtil.readDsFifo( INST_EXPDATA )
+    testUtil.readEot( )
+    testUtil.writeUsFifo( INST_STEP_0_0_TESTDATA_WITHOUT_WARN_FLG )
+    testUtil.writeEot( )
+    testUtil.readDsFifo( STEP_INST_EXPDATA_ERR_WTH_FFDC )
+    testUtil.readEot( )
+    testUtil.writeUsFifo( INST_STEP_0_1_TESTDATA_WITHOUT_WARN_FLG )
+    testUtil.writeEot( )
+    testUtil.readDsFifo( STEP_INST_EXPDATA_ERR_WTH_FFDC )
+    testUtil.readEot( )
+    testUtil.writeUsFifo( INST_STEP_0_2_TESTDATA_WITHOUT_WARN_FLG )
+    testUtil.writeEot( )
+    testUtil.readDsFifo( STEP_INST_EXPDATA_ERR_WTH_FFDC )
+    testUtil.readEot( )
+    testUtil.writeUsFifo( INST_STEP_0_3_TESTDATA_WITHOUT_WARN_FLG )
+    testUtil.writeEot( )
+    testUtil.readDsFifo( STEP_INST_EXPDATA_ERR_WTH_FFDC )
+    testUtil.readEot( )
+
+    #step all thread in core0
+    testUtil.writeUsFifo( INST_STEP0_ALL_TESTDATA_WITH_WARN_FLG )
+    testUtil.writeEot( )
+    testUtil.readDsFifo( INST_EXPDATA )
+    testUtil.readEot( )
+    testUtil.writeUsFifo( INST_STEP0_ALL_TESTDATA_WITHOUT_WARN_FLG )
+    testUtil.writeEot( )
+    testUtil.readDsFifo( STEP_INST_EXPDATA_ERR_WTH_FFDC )
+    testUtil.readEot( )
+
+    # Control Instruction Message - Sreset
+    testUtil.writeUsFifo( INST_SRESET_0_0_TESTDATA_WITH_WARN_FLG )
+    testUtil.writeEot( )
+    testUtil.readDsFifo( INST_EXPDATA )
+    testUtil.readEot( )
+    testUtil.writeUsFifo( INST_SRESET_0_1_TESTDATA_WITH_WARN_FLG )
+    testUtil.writeEot( )
+    testUtil.readDsFifo( INST_EXPDATA )
+    testUtil.readEot( )
+    testUtil.writeUsFifo( INST_SRESET_0_2_TESTDATA_WITH_WARN_FLG )
+    testUtil.writeEot( )
+    testUtil.readDsFifo( INST_EXPDATA )
+    testUtil.readEot( )
+    testUtil.writeUsFifo( INST_SRESET_0_3_TESTDATA_WITH_WARN_FLG )
+    testUtil.writeEot( )
+    testUtil.readDsFifo( INST_EXPDATA )
+    testUtil.readEot( )
+    testUtil.writeUsFifo( INST_SRESET_0_0_TESTDATA_WITHOUT_WARN_FLG )
+    testUtil.writeEot( )
+    testUtil.readDsFifo( INST_EXPDATA )
+    testUtil.readEot( )
+    testUtil.writeUsFifo( INST_SRESET_0_1_TESTDATA_WITHOUT_WARN_FLG )
+    testUtil.writeEot( )
+    testUtil.readDsFifo( INST_EXPDATA )
+    testUtil.readEot( )
+    testUtil.writeUsFifo( INST_SRESET_0_2_TESTDATA_WITHOUT_WARN_FLG )
+    testUtil.writeEot( )
+    testUtil.readDsFifo( INST_EXPDATA )
+    testUtil.readEot( )
+    testUtil.writeUsFifo( INST_SRESET_0_3_TESTDATA_WITHOUT_WARN_FLG )
+    testUtil.writeEot( )
+    testUtil.readDsFifo( INST_EXPDATA )
+    testUtil.readEot( )
+
+    #step all thread in core0
+    testUtil.writeUsFifo( INST_SRESET0_ALL_TESTDATA_WITH_WARN_FLG )
+    testUtil.writeEot( )
+    testUtil.readDsFifo( INST_EXPDATA )
+    testUtil.readEot( )
+    testUtil.writeUsFifo( INST_SRESET0_ALL_TESTDATA_WITHOUT_WARN_FLG )
+    testUtil.writeEot( )
+    testUtil.readDsFifo( INST_EXPDATA )
+    testUtil.readEot( )
+
+
+#-------------------------------------------------
+# Calling all test code
+#-------------------------------------------------
+main()
+
+if err:
+    print ("\nTest Suite completed with error(s)")
+    #sys.exit(1)
+else:
+    print ("\nTest Suite completed with no errors")
+    #sys.exit(0);
+
diff --git a/sbe/test/testCntlInstruction.xml b/sbe/test/testCntlInstruction.xml
new file mode 100755
index 00000000..1231ac86
--- /dev/null
+++ b/sbe/test/testCntlInstruction.xml
@@ -0,0 +1,7 @@
+<?xml version="1.0" encoding="UTF-8"?>
+
+      <testcase>
+          <simcmd>run-python-file targets/p9_nimbus/sbeTest/testCntlInstruction.py</simcmd>
+          <exitonerror>yes</exitonerror>
+      </testcase>
+
diff --git a/sbe/test/testGetCapabilities.py b/sbe/test/testGetCapabilities.py
index d7616eb7..4fb13a7f 100755
--- a/sbe/test/testGetCapabilities.py
+++ b/sbe/test/testGetCapabilities.py
@@ -21,7 +21,7 @@ EXPDATA2 = [0xa4,0x0,0x0,0x0f, #GetMemPba/PutMemPba/GetSramOcc/PutSramOcc
            0x0,0x0,0x0,0x0,
            0x0,0x0,0x0,0x0,
            0x0,0x0,0x0,0x0,
-           0x0,0x0,0x0,0x0,
+           0xa7,0x0,0x0,0x1, #  control Instruction
            0x00,0x0,0x0,0x0];
 
 EXPDATA3 = [0xa8,0x0,0x0,0x02, #getcapability
diff --git a/sbe/test/testIstep.xml b/sbe/test/testIstep.xml
index 07d92cd2..44de859a 100644
--- a/sbe/test/testIstep.xml
+++ b/sbe/test/testIstep.xml
@@ -261,6 +261,14 @@
           <simcmd>sbe-istep 4 31</simcmd>
           <exitonerror>yes</exitonerror>
       </testcase>
+      <testcase>
+          <simcmd>sbe-istep 5 1</simcmd>
+          <exitonerror>yes</exitonerror>
+      </testcase>
+      <testcase>
+          <simcmd>sbe-istep 5 2</simcmd>
+          <exitonerror>yes</exitonerror>
+      </testcase>
       <!-- Invalid Istep Test case -->
       <testcase>
           <simcmd>run-python-file targets/p9_nimbus/sbeTest/testIstepInvalid.py</simcmd>