Test code

Change-Id: If2e6a57017e6935cfdf93cebef810ddd7e59317a
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/17853
Tested-by: Jenkins Server
Reviewed-by: Amit J. Tendolkar <amit.tendolkar@in.ibm.com>
Tested-by: Amit J. Tendolkar <amit.tendolkar@in.ibm.com>

8 files changed, 267 insertions, 0 deletions

diff --git a/sbe/test/ffdc.xml b/sbe/test/ffdc.xml
new file mode 100755
index 00000000..1218f35d
--- /dev/null
+++ b/sbe/test/ffdc.xml
@@ -0,0 +1,15 @@
+<?xml version="1.0" encoding="UTF-8"?>
+
+    <test>
+    <subtest>
+        <testcase>
+            <simcmd>pipe \"p9Proc0.sbe.mibo_space.x (p9Proc0.sbe.ppe.sym g_pk_trace_buf_ptr) 0x2028\" \"sed 's/^p:0x........ //g' | sed 's/ ................$//g' | sed 's/ //g' | xxd -r -p> ppetrace.bin\"</simcmd>
+        </testcase>
+        <testcase>
+            <simcmd>p9Proc0.proc_fifo->upstream_hw_fifo</simcmd>
+        </testcase>
+        <testcase>
+            <simcmd>p9Proc0.proc_fifo->downstream_hw_fifo</simcmd>
+        </testcase>
+    </subtest>
+    </test>
diff --git a/sbe/test/test.xml b/sbe/test/test.xml
new file mode 100755
index 00000000..1bb0a263
--- /dev/null
+++ b/sbe/test/test.xml
@@ -0,0 +1,24 @@
+<?xml version="1.0" encoding="UTF-8"?>
+
+<integrationtest>
+	<platform startsimargs="--notar --norun">
+		<machine>%%machine%%</machine>
+
+        <test>
+            <!-- testcase>
+                <simcmd>new-symtable file = ~/workspace/sbe/obj/sbe_main.out name = sbe_main</simcmd>
+            </testcase>
+            <testcase>
+                <simcmd>@SIM_create_object('context', 'myppectx', [])</simcmd>
+            </testcase>
+            <testcase>
+                <simcmd>myppectx.symtable symtable = sbe_main</simcmd>
+            </testcase>
+            <testcase>
+                <simcmd>p9Proc0.sbe.ppe.set-context context = myppectx</simcmd>
+            </testcas -->
+            <include>../simics/targets/p9_nimbus/sbeTest/testIstep.xml</include>
+            <include>../simics/targets/p9_nimbus/sbeTest/testScom.xml</include>
+        </test>
+	</platform>
+</integrationtest>
diff --git a/sbe/test/testIstep.xml b/sbe/test/testIstep.xml
new file mode 100644
index 00000000..00983a3f
--- /dev/null
+++ b/sbe/test/testIstep.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0" encoding="UTF-8"?>
+
+      <!-- Positive Istep Test case -->
+      <testcase>
+          <simcmd>run-python-file targets/p9_nimbus/sbeTest/testIstepSuccess.py</simcmd>
+          <exitonerror>yes</exitonerror>
+      </testcase>
+      <!-- Invalid Istep Test case -->
+      <testcase>
+          <simcmd>run-python-file targets/p9_nimbus/sbeTest/testIstepInvalid.py</simcmd>
+          <exitonerror>yes</exitonerror>
+      </testcase>
diff --git a/sbe/test/testIstepInvalid.py b/sbe/test/testIstepInvalid.py
new file mode 100755
index 00000000..891ddecf
--- /dev/null
+++ b/sbe/test/testIstepInvalid.py
@@ -0,0 +1,34 @@
+import sys
+sys.path.append("targets/p9_nimbus/sbeTest" )
+import testUtil
+err = False
+#from testWrite import *
+
+TESTDATA = [0,0,0,3,
+            0,0,0xA1,0x01,
+            0,0x02,0x00,0x1]
+
+EXPDATA = [0xc0,0xde,0xa1,0x01,
+           0x0,0x2,0x0,0xa,
+           0x00,0x0,0x0,0x03];
+
+# MAIN Test Run Starts Here...
+#-------------------------------------------------
+def main( ):
+    testUtil.runCycles( 10000000 )
+    testUtil.writeUsFifo( TESTDATA )
+    testUtil.writeEot( )
+    testUtil.readDsFifo( EXPDATA )
+    testUtil.readEot( )
+#-------------------------------------------------
+# Calling all test code
+#-------------------------------------------------
+main()
+
+if err:
+    print ("\nTest Suite completed with error(s)")
+    #sys.exit(1)
+else:
+    print ("\nTest Suite completed with no errors")
+    #sys.exit(0);
+
diff --git a/sbe/test/testIstepSuccess.py b/sbe/test/testIstepSuccess.py
new file mode 100755
index 00000000..14d2e545
--- /dev/null
+++ b/sbe/test/testIstepSuccess.py
@@ -0,0 +1,34 @@
+import sys
+sys.path.append("targets/p9_nimbus/sbeTest" )
+import testUtil
+err = False
+#from testWrite import *
+
+TESTDATA = [0,0,0,3,
+            0,0,0xA1,0x01,
+            0,0x02,0x00,0x3]
+
+EXPDATA = [0xc0,0xde,0xa1,0x01,
+           0x0,0x0,0x0,0x0,
+           0x00,0x0,0x0,0x03];
+
+# MAIN Test Run Starts Here...
+#-------------------------------------------------
+def main( ):
+    testUtil.runCycles( 10000000 )
+    testUtil.writeUsFifo( TESTDATA )
+    testUtil.writeEot( )
+    testUtil.readDsFifo( EXPDATA )
+    testUtil.readEot( )
+#-------------------------------------------------
+# Calling all test code
+#-------------------------------------------------
+main()
+
+if err:
+    print ("\nTest Suite completed with error(s)")
+    #sys.exit(1)
+else:
+    print ("\nTest Suite completed with no errors")
+    #sys.exit(0);
+
diff --git a/sbe/test/testPutGetScom.py b/sbe/test/testPutGetScom.py
new file mode 100755
index 00000000..b6a7e74d
--- /dev/null
+++ b/sbe/test/testPutGetScom.py
@@ -0,0 +1,55 @@
+import sys
+sys.path.append("targets/p9_nimbus/sbeTest" )
+import testUtil
+err = False
+#from testWrite import *
+
+PUTSCOM_TESTDATA = [0,0,0,6,
+                    0,0,0xA2,0x02,
+                    0,0,0x0,0x00,
+                    0,0x02,0x00,0x14,
+                    0xde,0xca,0xff,0xee,
+                    0xf0,0xee,0xcc,0xff ]
+
+PUTSCOM_EXPDATA = [0xc0,0xde,0xa2,0x02,
+                   0x0,0x0,0x0,0x0,
+                   0x0,0x0,0x0,0x0,
+                   0x00,0x0,0x0,0x04];
+
+GETSCOM_TESTDATA = [0,0,0,4,
+                    0,0,0xA2,0x01,
+                    0,0,0x0,0x00,
+                    0,0x02,0x0,0x14]
+
+GETSCOM_EXPDATA = [0xde,0xca,0xff,0xee,
+                   0xf0,0xee,0xcc,0xff,
+                   0xc0,0xde,0xa2,0x01,
+                   0x0,0x0,0x0,0x0,
+                   0x0,0x0,0x0,0x0,
+                   0x00,0x0,0x0,0x04];
+
+# MAIN Test Run Starts Here...
+#-------------------------------------------------
+def main( ):
+    testUtil.runCycles( 10000000 )
+    testUtil.writeUsFifo( PUTSCOM_TESTDATA )
+    testUtil.writeEot( )
+    testUtil.readDsFifo( PUTSCOM_EXPDATA )
+    testUtil.readEot( )
+    testUtil.writeUsFifo( GETSCOM_TESTDATA )
+    testUtil.writeEot( )
+    testUtil.readDsFifo( GETSCOM_EXPDATA )
+    testUtil.readEot( )
+
+#-------------------------------------------------
+# Calling all test code
+#-------------------------------------------------
+main()
+
+if err:
+    print ("\nTest Suite completed with error(s)")
+    #sys.exit(1)
+else:
+    print ("\nTest Suite completed with no errors")
+    #sys.exit(0);
+
diff --git a/sbe/test/testScom.xml b/sbe/test/testScom.xml
new file mode 100755
index 00000000..01228e2a
--- /dev/null
+++ b/sbe/test/testScom.xml
@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="UTF-8"?>
+
+      <!-- Workaround to set clock regs. Once simics have fix, we can remove it -->
+      <testcase>
+          <simcmd>p9Proc0.proc_chip.invoke parallel_store LOGIC 0xffc50000 \"00000000_00000001\" 64</simcmd>
+      </testcase>
+      <!-- Write value to a register and than read it back -->
+      <testcase>
+          <simcmd>run-python-file targets/p9_nimbus/sbeTest/testPutGetScom.py</simcmd>
+          <exitonerror>yes</exitonerror>
+      </testcase>
diff --git a/sbe/test/testUtil.py b/sbe/test/testUtil.py
new file mode 100644
index 00000000..15c36b96
--- /dev/null
+++ b/sbe/test/testUtil.py
@@ -0,0 +1,82 @@
+import stest
+import time
+import conf
+from sim_commands import *
+
+#err = False
+lbus = conf.p9Proc0.proc_lbus_map
+stest.untrap_log(logtype="error")
+stest.untrap_log(logtype="info")
+def writeUsFifo( data):
+    """Main test Loop"""
+    print "Starting test. Data =", data
+    loopCount = len(data)/4;
+    for i in range (loopCount):
+        idx = i * 4;
+        write(lbus, 0x2400, (data[idx], data[idx+1], data[idx+2], data[idx+3]) )
+
+def readDsFifo(data):
+    """Main test Loop"""
+    print "Starting test. Data =", data
+    loopCount = len(data)/4;
+    for i in range (loopCount):
+        idx = i * 4;
+        stest.expect_equal(readEntry(lbus, 0x2440, 4), (data[idx], data[idx+1], data[idx+2], data[idx+3]))
+
+def writeEot():
+    write(lbus, 0x2408, (0, 0, 0, 1) )
+
+def write(obj, address, value ):
+    """ Write to memory space """
+    iface = SIM_get_interface(obj, "memory_space")
+    iface.write(None, address, value, 0x0)
+
+def readEot():
+    """ Read from memory space """
+    status = read(lbus, 0x2444, 4)
+    print "readEot status[3]",  status[3]
+    stest.expect_equal( (status[3] & 0x80), 0x80 );
+    read(lbus, 0x2440, 4)
+
+# This function will only read the entry but will not compare it
+# with anything. This can be used to flush out enteries.
+def readDsEntry(entryCount):
+    for i in range (entryCount):
+        readEntry(lbus, 0x2440, 4)
+
+def readEntry(obj, address, size):
+
+    """ Read from memory space """
+    loop = 1;
+    count = 0;
+    value = (0,0,0,0)
+    while( loop ):
+        status = read(lbus, 0x2444, 4)
+
+        if( status[1] & 0x0F):
+            # read entry
+            value = read(lbus, address, size)
+            loop = 0
+        else:
+            count = count + 1
+            runCycles(200000)
+            # This will cause  test to fail
+            stest.expect_true( count < 10 , "No data in FIFO")
+
+    return value
+
+def read(obj, address, size):
+    """ Read from memory space """
+    iface = SIM_get_interface(obj, "memory_space")
+    value = iface.read(None, address, size, 0x0)
+    print "address:", address
+    print "value:", value
+    return value
+
+def runCycles( cycles ):
+    if (not SIM_simics_is_running()):
+        syscmd   =   "run-cycles %d"%(cycles)
+        ( rc, out )  =   quiet_run_command( syscmd, output_modes.regular )
+        if ( rc ):
+            print "simics ERROR running %s: %d "%( syscmd, rc )
+