Remove dependency from stest module

stest is simics specific module and will not be available on other
platforms

Change-Id: I943254aa933ec98f926a11fc43c008e4ee3a6b03
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/21069
Tested-by: Jenkins Server
Reviewed-by: Basabjit Sengupta <basengup@in.ibm.com>
Reviewed-by: Amit J. Tendolkar <amit.tendolkar@in.ibm.com>

1 files changed, 34 insertions, 13 deletions

diff --git a/sbe/test/testUtil.py b/sbe/test/testUtil.py
index 15c36b96..3af06ffc 100644
--- a/sbe/test/testUtil.py
+++ b/sbe/test/testUtil.py
@@ -1,27 +1,22 @@
-import stest
 import time
 import conf
 from sim_commands import *
 
 #err = False
 lbus = conf.p9Proc0.proc_lbus_map
-stest.untrap_log(logtype="error")
-stest.untrap_log(logtype="info")
 def writeUsFifo( data):
     """Main test Loop"""
-    print "Starting test. Data =", data
     loopCount = len(data)/4;
     for i in range (loopCount):
         idx = i * 4;
-        write(lbus, 0x2400, (data[idx], data[idx+1], data[idx+2], data[idx+3]) )
+        writeEntry(lbus, 0x2400, (data[idx], data[idx+1], data[idx+2], data[idx+3]) )
 
 def readDsFifo(data):
     """Main test Loop"""
-    print "Starting test. Data =", data
     loopCount = len(data)/4;
     for i in range (loopCount):
         idx = i * 4;
-        stest.expect_equal(readEntry(lbus, 0x2440, 4), (data[idx], data[idx+1], data[idx+2], data[idx+3]))
+        checkEqual(readEntry(lbus, 0x2440, 4), (data[idx], data[idx+1], data[idx+2], data[idx+3]))
 
 def writeEot():
     write(lbus, 0x2408, (0, 0, 0, 1) )
@@ -34,8 +29,7 @@ def write(obj, address, value ):
 def readEot():
     """ Read from memory space """
     status = read(lbus, 0x2444, 4)
-    print "readEot status[3]",  status[3]
-    stest.expect_equal( (status[3] & 0x80), 0x80 );
+    checkEqual( (status[3] & 0x80), 0x80 );
     read(lbus, 0x2440, 4)
 
 # This function will only read the entry but will not compare it
@@ -44,6 +38,26 @@ def readDsEntry(entryCount):
     for i in range (entryCount):
         readEntry(lbus, 0x2440, 4)
 
+def writeEntry(obj, address, value ):
+
+    loop = 1;
+    count = 0;
+    while( loop ):
+        status = read(lbus, 0x2404, 4)  # Address 0x2404: Upstream Fifo Status
+
+        if( status[2] & 0x02):
+            count = count + 1
+            runCycles(200000)
+            # This will cause  test to fail
+            if(count > 10):
+                raise Exception('Timeout. FIFO FULL');
+        else:
+            # write entry
+            write(obj, address, value)
+            loop = 0
+
+    return value
+
 def readEntry(obj, address, size):
 
     """ Read from memory space """
@@ -51,7 +65,7 @@ def readEntry(obj, address, size):
     count = 0;
     value = (0,0,0,0)
     while( loop ):
-        status = read(lbus, 0x2444, 4)
+        status = read(lbus, 0x2444, 4)  # Address 0x2444: Downstream Fifo Status
 
         if( status[1] & 0x0F):
             # read entry
@@ -61,7 +75,8 @@ def readEntry(obj, address, size):
             count = count + 1
             runCycles(200000)
             # This will cause  test to fail
-            stest.expect_true( count < 10 , "No data in FIFO")
+            if(count > 10):
+                raise Exception('Timeout. Empty FIFO');
 
     return value
 
@@ -69,8 +84,6 @@ def read(obj, address, size):
     """ Read from memory space """
     iface = SIM_get_interface(obj, "memory_space")
     value = iface.read(None, address, size, 0x0)
-    print "address:", address
-    print "value:", value
     return value
 
 def runCycles( cycles ):
@@ -80,3 +93,11 @@ def runCycles( cycles ):
         if ( rc ):
             print "simics ERROR running %s: %d "%( syscmd, rc )
 
+def checkEqual( data, expdata ):
+    """ Throw exception if data is not equal """
+    if( cmp(data, expdata )):
+        print "Eqality check failed"
+        print "Data:", data
+        print "Expected Data", expdata
+        raise Exception('data mistmach');
+