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| author | Nick Klazynski <jklazyns@us.ibm.com> | 2016-08-30 15:04:44 -0500 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2016-09-01 02:19:17 -0400 |
| commit | f559f31a1d92982b8bfc07c21a496a62e9ba9f5d (patch) | |
| tree | a37025caa36f165db77ac46d210511141eaf6426 /import | |
| parent | 57b78f3c486c47f8e9e2bb6773236eaef9324eae (diff) | |
| download | talos-sbe-f559f31a1d92982b8bfc07c21a496a62e9ba9f5d.tar.gz talos-sbe-f559f31a1d92982b8bfc07c21a496a62e9ba9f5d.zip | |
AVP_MODE needs to be set for cache-contained and runn. Moving to startclocks.
Change-Id: I05bc05e17ba0c0e02a4cc8daf085bf6d64fec90d
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29002
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: YUE DU <daviddu@us.ibm.com>
Reviewed-by: Benjamin Gass <bgass@us.ibm.com>
Dev-Ready: James N. Klazynski <jklazyns@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29003
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'import')
| -rw-r--r-- | import/chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.C | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/import/chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.C b/import/chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.C index 111526c6..3cccb8b5 100644 --- a/import/chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.C +++ b/import/chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.C @@ -112,6 +112,13 @@ p9_hcd_core_startclocks( // Prepare to start core clocks // ---------------------------- + if (l_attr_system_ipl_phase == + fapi2::ENUM_ATTR_SYSTEM_IPL_PHASE_CACHE_CONTAINED) + { + FAPI_DBG("Set CPLT_CTRL0[AVP_MODE] for cache-contained execution"); + FAPI_TRY(putScom(i_target, C_CPLT_CTRL0_OR, MASK_SET(5))); + } + /// @todo add DD1 attribute control FAPI_DBG("DD1 only: set sdis_n(flushing LCBES condition workaround"); FAPI_TRY(putScom(i_target, C_CPLT_CONF0_OR, MASK_SET(34))); @@ -256,7 +263,8 @@ p9_hcd_core_startclocks( FAPI_DBG("Drop flushmode_inhibit via CPLT_CTRL0[2]"); FAPI_TRY(putScom(i_target, C_CPLT_CTRL0_CLEAR, MASK_SET(2))); - if (!l_attr_runn_mode && l_attr_system_ipl_phase != 0x4/*CACHE_CONTAINED*/) + if (!l_attr_runn_mode && l_attr_system_ipl_phase != + fapi2::ENUM_ATTR_SYSTEM_IPL_PHASE_CACHE_CONTAINED) { FAPI_DBG("Drop Core-L2/CC Quiesces via CME_SCOM_SICR[6,8]/[7,9]"); FAPI_TRY(putScom(l_quad, |
