diff options
| author | Yue Du <daviddu@us.ibm.com> | 2016-02-24 23:27:38 -0600 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2016-08-16 11:56:49 -0400 |
| commit | d2a07458f4b1767cd3da511b9f3d657d3d65b6f5 (patch) | |
| tree | c3800bd33bfa029b887c02750ac4ae3482412246 /import | |
| parent | 0a6dc36fb0c2cff9841a52081a5121f7646bbf66 (diff) | |
| download | talos-sbe-d2a07458f4b1767cd3da511b9f3d657d3d65b6f5.tar.gz talos-sbe-d2a07458f4b1767cd3da511b9f3d657d3d65b6f5.zip | |
Combined Stop/PState Cme Image + unified interrupt handler
Change-Id: Ie954197008f1a35bd8336c9d921f55165ec52207
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/20857
Tested-by: Jenkins Server
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28285
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'import')
| -rw-r--r-- | import/chips/p9/procedures/ppe/pk/std/std_common.h | 10 | ||||
| -rw-r--r-- | import/chips/p9/procedures/ppe/pk/std/std_irq.h | 27 |
2 files changed, 37 insertions, 0 deletions
diff --git a/import/chips/p9/procedures/ppe/pk/std/std_common.h b/import/chips/p9/procedures/ppe/pk/std/std_common.h index 358be9f1..a1f52eda 100644 --- a/import/chips/p9/procedures/ppe/pk/std/std_common.h +++ b/import/chips/p9/procedures/ppe/pk/std/std_common.h @@ -54,9 +54,19 @@ /// /// r1, r2, r3, and r13 must not be modified. All other registers may be used. /// +/// The pk_unified_irq_prty_mask_handler routine MUST return the task priority +/// interrupt vector in d5. +/// .macro hwmacro_get_ext_irq +#ifdef UNIFIED_IRQ_HANDLER_CME + // Unified approach. + _liw r5, pk_unified_irq_prty_mask_handler + mtlr r5 + blrl // On return, d5 contains task prty irq vec. +#else _lvdg d5, STD_LCL_EISTR #load the 64bit interrupt status into d5 +#endif cntlzw r4, r5 cmpwible r4, 31, call_external_irq_handler #branch if irq is lt or eq to 31 diff --git a/import/chips/p9/procedures/ppe/pk/std/std_irq.h b/import/chips/p9/procedures/ppe/pk/std/std_irq.h index fb71ae09..4af55745 100644 --- a/import/chips/p9/procedures/ppe/pk/std/std_irq.h +++ b/import/chips/p9/procedures/ppe/pk/std/std_irq.h @@ -59,6 +59,14 @@ pk_irq_enable(PkIrqId irq) out64(STD_LCL_EIMR_CLR, STD_IRQ_MASK64(irq)); } +/// Enable a vector of interrupts by clearing the mask bits. + +UNLESS__PPE42_IRQ_CORE_C__(extern) +inline void +pk_irq_vec_enable(uint64_t irq_vec_mask) +{ + out64(STD_LCL_EIMR_CLR, irq_vec_mask); +} /// Disable an interrupt by setting the mask bit. @@ -69,6 +77,15 @@ pk_irq_disable(PkIrqId irq) out64(STD_LCL_EIMR_OR, STD_IRQ_MASK64(irq)); } +/// Disable a vector of interrupts by setting the mask bits. + +UNLESS__PPE42_IRQ_CORE_C__(extern) +inline void +pk_irq_vec_disable(uint64_t irq_vec_mask) +{ + out64(STD_LCL_EIMR_OR, irq_vec_mask); +} + /// Clear interrupt status with an CLR mask. Only meaningful for /// edge-triggered interrupts. @@ -81,6 +98,16 @@ pk_irq_status_clear(PkIrqId irq) } +/// Clear a vector of interrupts status with an CLR mask. Only meaningful for +/// edge-triggered interrupts. + +UNLESS__PPE42_IRQ_CORE_C__(extern) +inline void +pk_irq_vec_status_clear(uint64_t irq_vec_mask) +{ + out64(STD_LCL_EISR_CLR, irq_vec_mask); +} + /// Get IRQ status as a 0 or non-0 integer UNLESS__PPE42_IRQ_CORE_C__(extern) |
