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| author | Joachim Fenkes <fenkes@de.ibm.com> | 2016-07-07 17:41:44 +0200 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2016-08-11 00:51:28 -0400 |
| commit | aeb890bb01fdd8b3aece4eccb9ff9d260b0d36d6 (patch) | |
| tree | b376977abc0eb8ef6b15f5aaeed0e6640ce35ce8 /import | |
| parent | c3910bf8ada7123ee4847bbf29122fb7dc7b3be5 (diff) | |
| download | talos-sbe-aeb890bb01fdd8b3aece4eccb9ff9d260b0d36d6.tar.gz talos-sbe-aeb890bb01fdd8b3aece4eccb9ff9d260b0d36d6.zip | |
p9_sbe_chiplet_reset: Change NX_1 hang pulse period to 68s
The NX logic requires the NX_1 hang pulse (N0 hang pulse 2) to fire
every 68s, but it used to be set up for half that, so change the
procedure to use the correct value of 35.
Change-Id: I2b8d81717a5b9d1f05c7c3d3f38403c89de82648
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/26717
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Abhishek Agarwal <abagarw8@in.ibm.com>
Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/26721
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'import')
| -rw-r--r-- | import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C | 4 | ||||
| -rw-r--r-- | import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H | 1 |
2 files changed, 3 insertions, 2 deletions
diff --git a/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C b/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C index f6272ec7..5021966c 100644 --- a/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C +++ b/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C @@ -1020,8 +1020,8 @@ static fapi2::ReturnCode p9_sbe_chiplet_reset_nest_hang_cnt_setup( l_data64.clearBit<6>(); //HANG_PULSE_1_REG.SUPPRESS_HANG_1 = 0 FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_1_REG, l_data64)); //Setting HANG_PULSE_2_REG register value (Setting all fields) - //HANG_PULSE_2_REG.HANG_PULSE_REG_2 = p9SbeChipletReset::HANG_PULSE_0X22 - l_data64.insertFromRight<0, 6>(p9SbeChipletReset::HANG_PULSE_0X22); + //HANG_PULSE_2_REG.HANG_PULSE_REG_2 = p9SbeChipletReset::HANG_PULSE_0X23 + l_data64.insertFromRight<0, 6>(p9SbeChipletReset::HANG_PULSE_0X23); l_data64.clearBit<6>(); //HANG_PULSE_2_REG.SUPPRESS_HANG_2 = 0 FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_2_REG, l_data64)); //Setting HANG_PULSE_3_REG register value (Setting all fields) diff --git a/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H b/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H index 0d416ace..e083588c 100644 --- a/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H +++ b/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H @@ -62,6 +62,7 @@ enum P9_SBE_CHIPLET_RESET_Public_Constants HANG_PULSE_0X17 = 0x17, HANG_PULSE_0X18 = 0x18, HANG_PULSE_0X22 = 0x22, + HANG_PULSE_0X23 = 0x23, HANG_PULSE_0X13 = 0x13, HANG_PULSE_0X03 = 0x03, OPCG_ALIGN_SETTING = 0x5000000000003020ull, |
