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| author | Yue Du <daviddu@us.ibm.com> | 2016-08-11 13:09:29 -0500 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2016-08-17 09:59:09 -0400 |
| commit | 8f236340fbc886657730a2e9af731e4de80a7c1a (patch) | |
| tree | 8dea63f02ea4c04867cc6d63ad203ded1c64a69b /import | |
| parent | 6dcd83fa85801d3363420c7d30cd3272b21d73da (diff) | |
| download | talos-sbe-8f236340fbc886657730a2e9af731e4de80a7c1a.tar.gz talos-sbe-8f236340fbc886657730a2e9af731e4de80a7c1a.zip | |
CORE/CACHE: istep4 functional fix collection
Change-Id: I27093040dc03cd88d9b9e67831c216cba7a1996c
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28170
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Abhishek Agarwal <abagarw8@in.ibm.com>
Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com>
Reviewed-by: Sangeetha T S <sangeet2@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28172
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'import')
| -rw-r--r-- | import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.C | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.C b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.C index 1146b86d..744f0ae9 100644 --- a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.C +++ b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.C @@ -105,6 +105,9 @@ p9_hcd_cache_dpll_setup( l_data64.flush<0>().setBit<2>().insertFromRight<6, 10>(0x40); FAPI_TRY(putScom(i_target, EQ_QPPM_DPLL_CTRL_OR, l_data64)); + FAPI_DBG("Drop flushmode_inhibit via CPLT_CTRL0[2]"); + FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL0_CLEAR, MASK_SET(2))); + FAPI_DBG("Drop DPLL test mode and reset via NET_CTRL0[3,4]"); FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WAND, MASK_AND(3, 2, 0))); @@ -176,6 +179,9 @@ p9_hcd_cache_dpll_setup( FAPI_DBG("Drop DPLL ff_bypass via QPPM_DPLL_CTRL[2]"); FAPI_TRY(putScom(i_target, EQ_QPPM_DPLL_CTRL_CLEAR, MASK_SET(2))); + FAPI_DBG("Assert flushmode_inhibit via CPLT_CTRL0[2]"); + FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL0_OR, MASK_SET(2))); + FAPI_DBG("Set scan ratio to 4:1 in non-bypass mode via OPCG_ALIGN[47-51]"); FAPI_TRY(getScom(i_target, EQ_OPCG_ALIGN, l_data64)); l_data64.insertFromRight<47, 5>(0x3); |
