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authorGreg Still <stillgs@us.ibm.com>2016-05-19 23:51:53 -0500
committerSachin Gupta <sgupta2m@in.ibm.com>2016-08-25 23:59:37 -0400
commit43aff307f8eb7950378c1400d14613a4776cca15 (patch)
tree5d7c27df9cf12eae076ea0d2794502c50299cb8d /import
parent4b0f5a44e169e6a5510b735c76805a88c33b95d4 (diff)
downloadtalos-sbe-43aff307f8eb7950378c1400d14613a4776cca15.tar.gz
talos-sbe-43aff307f8eb7950378c1400d14613a4776cca15.zip
PK_PANIC using trap
Change-Id: I5f516c5e8d4ae77467e209d283799e2e88341dc9 RTC: 147211 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24845 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28350 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Diffstat (limited to 'import')
-rw-r--r--import/chips/p9/procedures/ppe/pk/kernel/pk_api.h74
-rw-r--r--import/chips/p9/procedures/ppe/pk/ppe42/pk_panic_codes.h314
-rw-r--r--import/chips/p9/procedures/ppe/pk/ppe42/ppe42.h138
-rw-r--r--import/chips/p9/procedures/ppe/pk/ppe42/ppe42_boot.S2
-rw-r--r--import/chips/p9/procedures/ppe/pk/ppe42/ppe42_irq.h9
-rw-r--r--import/chips/p9/procedures/ppe/pk/ppe42/ppe42_irq_core.c2
-rw-r--r--import/chips/p9/procedures/ppe/pk/ppe42/ppe42_spr.h8
7 files changed, 382 insertions, 165 deletions
diff --git a/import/chips/p9/procedures/ppe/pk/kernel/pk_api.h b/import/chips/p9/procedures/ppe/pk/kernel/pk_api.h
index c3308da9..b094519c 100644
--- a/import/chips/p9/procedures/ppe/pk/kernel/pk_api.h
+++ b/import/chips/p9/procedures/ppe/pk/kernel/pk_api.h
@@ -54,78 +54,8 @@
// API return codes
#define PK_OK 0
-#define PK_ILLEGAL_CONTEXT_THREAD_CONTEXT 0x00779002
-#define PK_ILLEGAL_CONTEXT_INTERRUPT_CONTEXT 0x00779003
-#define PK_ILLEGAL_CONTEXT_THREAD 0x00779004
-#define PK_ILLEGAL_CONTEXT_TIMER 0x00779005
-#define PK_INVALID_THREAD_AT_RESUME1 0x00779007
-#define PK_INVALID_THREAD_AT_RESUME2 0x00779008
-#define PK_INVALID_THREAD_AT_SUSPEND1 0x00779009
-#define PK_INVALID_THREAD_AT_SUSPEND2 0x0077900a
-#define PK_INVALID_THREAD_AT_DELETE 0x0077900b
-#define PK_INVALID_THREAD_AT_INFO 0x0077900c
-#define PK_INVALID_THREAD_AT_CHANGE 0x0077900d
-#define PK_INVALID_THREAD_AT_SWAP1 0x0077900e
-#define PK_INVALID_THREAD_AT_SWAP2 0x0077900f
-#define PK_INVALID_THREAD_AT_CREATE 0x00779010
-#define PK_INVALID_SEMAPHORE_AT_POST 0x00779011
-#define PK_INVALID_SEMAPHORE_AT_PEND 0x00779012
-#define PK_INVALID_SEMAPHORE_AT_RELEASE 0x00779013
-#define PK_INVALID_SEMAPHORE_AT_INFO 0x00779014
-#define PK_INVALID_SEMAPHORE_AT_CREATE 0x00779015
-#define PK_INVALID_TIMER_AT_SCHEDULE 0x00779016
-#define PK_INVALID_TIMER_AT_CANCEL 0x00779017
-#define PK_INVALID_TIMER_AT_INFO 0x00779018
-#define PK_INVALID_TIMER_AT_CREATE 0x00779019
-#define PK_INVALID_ARGUMENT_IRQ_SETUP 0x0077901a
-#define PK_INVALID_ARGUMENT_IRQ_HANDLER 0x0077901b
-#define PK_INVALID_ARGUMENT_INTERRUPT 0x00779024
-#define PK_INVALID_ARGUMENT_CONTEXT_SET 0x00779025
-#define PK_INVALID_ARGUMENT_CONTEXT_GET 0x00779026
-#define PK_INVALID_ARGUMENT_FIT 0x00779027
-#define PK_INVALID_ARGUMENT_WATCHDOG 0x00779028
-#define PK_INVALID_ARGUMENT_INIT 0x00779029
-#define PK_INVALID_ARGUMENT_SEMAPHORE 0x0077902a
-#define PK_INVALID_ARGUMENT_THREAD_CHANGE 0x0077902b
-#define PK_INVALID_ARGUMENT_THREAD_PRIORITY 0x0077902c
-#define PK_INVALID_ARGUMENT_THREAD1 0x0077902d
-#define PK_INVALID_ARGUMENT_THREAD2 0x0077902e
-#define PK_INVALID_ARGUMENT_THREAD3 0x0077902f
-#define PK_STACK_OVERFLOW 0x00779030
-#define PK_TIMER_ACTIVE 0x00779031
-#define PK_TIMER_NOT_ACTIVE 0x00779032
-#define PK_PRIORITY_IN_USE_AT_RESUME 0x00779033
-#define PK_PRIORITY_IN_USE_AT_CHANGE 0x00779034
-#define PK_PRIORITY_IN_USE_AT_SWAP 0x00779035
-#define PK_SEMAPHORE_OVERFLOW 0x00779036
-#define PK_SEMAPHORE_PEND_NO_WAIT 0x00779037
-#define PK_SEMAPHORE_PEND_TIMED_OUT 0x00779038
-#define PK_SEMAPHORE_PEND_WOULD_BLOCK 0x00779039
-#define PK_INVALID_DEQUE_SENTINEL 0x0077903a
-#define PK_INVALID_DEQUE_ELEMENT 0x0077903b
-#define PK_INVALID_OBJECT 0x0077903c
-
-// Kernel panics
-
-#define PK_NO_TIMER_SUPPORT 0x0077903d
-#define PK_START_THREADS_RETURNED 0x0077903e
-#define PK_UNIMPLEMENTED 0x0077903f
-#define PK_SCHEDULING_INVARIANT 0x00779040
-#define PK_TIMER_HANDLER_INVARIANT 0x00779041
-#define PK_THREAD_TIMEOUT_STATE 0x00779045
-
-// Application-level panic offsets
-// (Use these as offsets for your application code panics and keep
-// track of them locally in your application code domain, including
-// sharing the panic defines with other developers making codes
-// for the same engine.)
-
-#define PK_APP_OFFSET_SBE 0x0077a000
-#define PK_APP_OFFSET_GPE0 0x0077b000
-#define PK_APP_OFFSET_GPE1 0x0077c000
-#define PK_APP_OFFSET_GPE2 0x0077d000
-#define PK_APP_OFFSET_GPE3 0x0077e000
-#define PK_APP_OFFSET_CME 0x0077f000
+
+/// @see pk_panic_codes.h for valid return/panic codes
/// \defgroup pk_thread_states PK Thread States
///
diff --git a/import/chips/p9/procedures/ppe/pk/ppe42/pk_panic_codes.h b/import/chips/p9/procedures/ppe/pk/ppe42/pk_panic_codes.h
index dd794291..0e079657 100644
--- a/import/chips/p9/procedures/ppe/pk/ppe42/pk_panic_codes.h
+++ b/import/chips/p9/procedures/ppe/pk/ppe42/pk_panic_codes.h
@@ -22,9 +22,319 @@
/* permissions and limitations under the License. */
/* */
/* IBM_PROLOG_END_TAG */
-// Preparation for new file for mirroring to ppe repository
-// RTC 147211 PK_PANIC using trap
#ifndef __PK_PANIC_CODES_H__
#define __PK_PANIC_CODES_H__
+// On PPE42, PANIC codes are stored as part of the trap word instruction.
+// tw 31, RA, RB Where RA and RB would used to encode the trap code.
+// There are 16 valid gprs on PP42, so this gives 256 possible trap codes.
+// The trap code is defined as a two byte code defined as 0xYYZZ where YY
+// is encoded into the RA field and ZZ is incoded into the RB field
+// YY and ZZ are limited to the values:
+// 00,01,02,03,04,05,06,07,08,09,0a,0d,1c,1d,1e,1f (valid gpr ids)
+//
+// To add a new panic code, select an unused values and rename it.
+// This enum contains all the valid values that can be used. Using a
+// panic code not in this list will result in a compiler/assembler error.
+#ifndef __ASSEMBLER__
+
+typedef enum
+{
+ PPE42_MACHINE_CHECK_PANIC = 0x0001,
+ PPE42_DATA_STORAGE_PANIC = 0x0002,
+ PPE42_INSTRUCTION_STORAGE_PANIC = 0x0003,
+ PPE42_DATA_ALIGNMENT_PANIC = 0x0004,
+ PK_BOOT_VECTORS_NOT_ALIGNED = 0x0005,
+ PK_DEFAULT_IRQ_HANDLER = 0x0006,
+ PK_DEFAULT_SPECIAL_HANDLER = 0x0007,
+ PPE42_PHANTOM_INTERRUPT = 0x0008,
+ PPE42_ILLEGAL_INSTRUCTION = 0x0009,
+ PK_UNUSED_000a = 0x000a,
+ PK_UNUSED_000d = 0x000d,
+ PK_UNUSED_001c = 0x001c,
+ PK_UNUSED_001d = 0x001d,
+ PK_UNUSED_001e = 0x001e,
+ PK_UNUSED_001f = 0x001f,
+
+ // API return codes
+ PK_ILLEGAL_CONTEXT_THREAD_CONTEXT = 0x0100,
+ PK_ILLEGAL_CONTEXT_INTERRUPT_CONTEXT = 0x0101,
+ PK_ILLEGAL_CONTEXT_THREAD = 0x0102,
+ PK_ILLEGAL_CONTEXT_TIMER = 0x0103,
+ PK_INVALID_THREAD_AT_RESUME1 = 0x0104,
+ PK_INVALID_THREAD_AT_RESUME2 = 0x0105,
+ PK_INVALID_THREAD_AT_SUSPEND1 = 0x0106,
+ PK_INVALID_THREAD_AT_SUSPEND2 = 0x0107,
+ PK_INVALID_THREAD_AT_DELETE = 0x0108,
+ PK_INVALID_THREAD_AT_INFO = 0x0109,
+ PK_INVALID_THREAD_AT_CHANGE = 0x010a,
+ PK_INVALID_THREAD_AT_SWAP1 = 0x010d,
+ PK_INVALID_THREAD_AT_SWAP2 = 0x011c,
+ PK_INVALID_THREAD_AT_CREATE = 0x011d,
+ PK_INVALID_SEMAPHORE_AT_POST = 0x011e,
+ PK_INVALID_SEMAPHORE_AT_PEND = 0x011f,
+ PK_INVALID_SEMAPHORE_AT_RELEASE = 0x0200,
+ PK_INVALID_SEMAPHORE_AT_INFO = 0x0201,
+ PK_INVALID_SEMAPHORE_AT_CREATE = 0x0202,
+ PK_INVALID_TIMER_AT_SCHEDULE = 0x0203,
+ PK_INVALID_TIMER_AT_CANCEL = 0x0204,
+ PK_INVALID_TIMER_AT_INFO = 0x0205,
+ PK_INVALID_TIMER_AT_CREATE = 0x0206,
+ PK_INVALID_ARGUMENT_IRQ_SETUP = 0x0207,
+ PK_INVALID_ARGUMENT_IRQ_HANDLER = 0x0208,
+ PK_INVALID_ARGUMENT_INTERRUPT = 0x0209,
+ PK_INVALID_ARGUMENT_CONTEXT_SET = 0x020a,
+ PK_INVALID_ARGUMENT_CONTEXT_GET = 0x020d,
+ PK_INVALID_ARGUMENT_FIT = 0x021c,
+ PK_INVALID_ARGUMENT_WATCHDOG = 0x021d,
+ PK_INVALID_ARGUMENT_INIT = 0x021e,
+ PK_INVALID_ARGUMENT_SEMAPHORE = 0x021f,
+ PK_INVALID_ARGUMENT_THREAD_CHANGE = 0x0300,
+ PK_INVALID_ARGUMENT_THREAD_PRIORITY = 0x0301,
+ PK_INVALID_ARGUMENT_THREAD1 = 0x0302,
+ PK_INVALID_ARGUMENT_THREAD2 = 0x0303,
+ PK_INVALID_ARGUMENT_THREAD3 = 0x0304,
+ PK_STACK_OVERFLOW = 0x0305,
+ PK_TIMER_ACTIVE = 0x0306,
+ PK_TIMER_NOT_ACTIVE = 0x0307,
+ PK_PRIORITY_IN_USE_AT_RESUME = 0x0308,
+ PK_PRIORITY_IN_USE_AT_CHANGE = 0x0309,
+ PK_PRIORITY_IN_USE_AT_SWAP = 0x030a,
+ PK_SEMAPHORE_OVERFLOW = 0x030d,
+ PK_SEMAPHORE_PEND_NO_WAIT = 0x031c,
+ PK_SEMAPHORE_PEND_TIMED_OUT = 0x031d,
+ PK_SEMAPHORE_PEND_WOULD_BLOCK = 0x031e,
+ PK_INVALID_DEQUE_SENTINEL = 0x031f,
+ PK_INVALID_DEQUE_ELEMENT = 0x0400,
+ PK_INVALID_OBJECT = 0x0401,
+
+ // PK Kernel panics
+ PK_NO_TIMER_SUPPORT = 0x0402,
+ PK_START_THREADS_RETURNED = 0x0403,
+ PK_UNIMPLEMENTED = 0x0404,
+ PK_SCHEDULING_INVARIANT = 0x0405,
+ PK_TIMER_HANDLER_INVARIANT = 0x0406,
+ PK_THREAD_TIMEOUT_STATE = 0x0407,
+
+ // PK
+ PK_UNUSED_0408 = 0x0408,
+ PK_UNUSED_0409 = 0x0409,
+ PK_UNUSED_040a = 0x040a,
+ PK_UNUSED_040d = 0x040d,
+ PK_UNUSED_041c = 0x041c,
+ PK_UNUSED_041d = 0x041d,
+ PK_UNUSED_041e = 0x041e,
+ PK_UNUSED_041f = 0x041f,
+
+ // Sync panic codes
+ SYNC_INVALID_OBJECT = 0x0500,
+ SYNC_INVALID_ARGUMENT = 0x0501,
+ SYNC_BARRIER_PEND_TIMED_OUT = 0x0502,
+ SYNC_BARRIER_OVERFLOW = 0x0503,
+ SYNC_BARRIER_UNDERFLOW = 0x0504,
+ SYNC_BARRIER_INVARIANT = 0x0505,
+ SYNC_SHARED_UNDERFLOW = 0x0506,
+
+ OCCHW_INSTANCE_MISMATCH = 0x0507,
+ OCCHW_IRQ_ROUTING_ERROR = 0x0508,
+ OCCHW_XIR_INVALID_POINTER = 0x0509,
+ OCCHW_XIR_INVALID_GPE = 0x050a,
+
+ PK_UNUSED_050d = 0x050d,
+ PK_UNUSED_051c = 0x051c,
+ PK_UNUSED_051d = 0x051d,
+ PK_UNUSED_051e = 0x051e,
+ PK_UNUSED_051f = 0x051f,
+
+ PK_UNUSED_0600 = 0x0600,
+ PK_UNUSED_0601 = 0x0601,
+ PK_UNUSED_0602 = 0x0602,
+ PK_UNUSED_0603 = 0x0603,
+ PK_UNUSED_0604 = 0x0604,
+ PK_UNUSED_0605 = 0x0605,
+ PK_UNUSED_0606 = 0x0606,
+ PK_UNUSED_0607 = 0x0607,
+ PK_UNUSED_0608 = 0x0608,
+ PK_UNUSED_0609 = 0x0609,
+ PK_UNUSED_060a = 0x060a,
+ PK_UNUSED_060d = 0x060d,
+ PK_UNUSED_061c = 0x061c,
+ PK_UNUSED_061d = 0x061d,
+ PK_UNUSED_061e = 0x061e,
+ PK_UNUSED_061f = 0x061f,
+
+ PK_UNUSED_0700 = 0x0700,
+ PK_UNUSED_0701 = 0x0701,
+ PK_UNUSED_0702 = 0x0702,
+ PK_UNUSED_0703 = 0x0703,
+ PK_UNUSED_0704 = 0x0704,
+ PK_UNUSED_0705 = 0x0705,
+ PK_UNUSED_0706 = 0x0706,
+ PK_UNUSED_0707 = 0x0707,
+ PK_UNUSED_0708 = 0x0708,
+ PK_UNUSED_0709 = 0x0709,
+ PK_UNUSED_070a = 0x070a,
+ PK_UNUSED_070d = 0x070d,
+ PK_UNUSED_071c = 0x071c,
+ PK_UNUSED_071d = 0x071d,
+ PK_UNUSED_071e = 0x071e,
+ PK_UNUSED_071f = 0x071f,
+
+ PK_UNUSED_0800 = 0x0800,
+ PK_UNUSED_0801 = 0x0801,
+ PK_UNUSED_0802 = 0x0802,
+ PK_UNUSED_0803 = 0x0803,
+ PK_UNUSED_0804 = 0x0804,
+ PK_UNUSED_0805 = 0x0805,
+ PK_UNUSED_0806 = 0x0806,
+ PK_UNUSED_0807 = 0x0807,
+ PK_UNUSED_0808 = 0x0808,
+ PK_UNUSED_0809 = 0x0809,
+ PK_UNUSED_080a = 0x080a,
+ PK_UNUSED_080d = 0x080d,
+ PK_UNUSED_081c = 0x081c,
+ PK_UNUSED_081d = 0x081d,
+ PK_UNUSED_081e = 0x081e,
+ PK_UNUSED_081f = 0x081f,
+
+ PK_UNUSED_0900 = 0x0900,
+ PK_UNUSED_0901 = 0x0901,
+ PK_UNUSED_0902 = 0x0902,
+ PK_UNUSED_0903 = 0x0903,
+ PK_UNUSED_0904 = 0x0904,
+ PK_UNUSED_0905 = 0x0905,
+ PK_UNUSED_0906 = 0x0906,
+ PK_UNUSED_0907 = 0x0907,
+ PK_UNUSED_0908 = 0x0908,
+ PK_UNUSED_0909 = 0x0909,
+ PK_UNUSED_090a = 0x090a,
+ PK_UNUSED_090d = 0x090d,
+ PK_UNUSED_091c = 0x091c,
+ PK_UNUSED_091d = 0x091d,
+ PK_UNUSED_091e = 0x091e,
+ PK_UNUSED_091f = 0x091f,
+
+ PK_UNUSED_0a00 = 0x0a00,
+ PK_UNUSED_0a01 = 0x0a01,
+ PK_UNUSED_0a02 = 0x0a02,
+ PK_UNUSED_0a03 = 0x0a03,
+ PK_UNUSED_0a04 = 0x0a04,
+ PK_UNUSED_0a05 = 0x0a05,
+ PK_UNUSED_0a06 = 0x0a06,
+ PK_UNUSED_0a07 = 0x0a07,
+ PK_UNUSED_0a08 = 0x0a08,
+ PK_UNUSED_0a09 = 0x0a09,
+ PK_UNUSED_0a0a = 0x0a0a,
+ PK_UNUSED_0a0d = 0x0a0d,
+ PK_UNUSED_0a1c = 0x0a1c,
+ PK_UNUSED_0a1d = 0x0a1d,
+ PK_UNUSED_0a1e = 0x0a1e,
+ PK_UNUSED_0a1f = 0x0a1f,
+
+ PK_UNUSED_0d00 = 0x0d00,
+ PK_UNUSED_0d01 = 0x0d01,
+ PK_UNUSED_0d02 = 0x0d02,
+ PK_UNUSED_0d03 = 0x0d03,
+ PK_UNUSED_0d04 = 0x0d04,
+ PK_UNUSED_0d05 = 0x0d05,
+ PK_UNUSED_0d06 = 0x0d06,
+ PK_UNUSED_0d07 = 0x0d07,
+ PK_UNUSED_0d08 = 0x0d08,
+ PK_UNUSED_0d09 = 0x0d09,
+ PK_UNUSED_0d0a = 0x0d0a,
+ PK_UNUSED_0d0d = 0x0d0d,
+ PK_UNUSED_0d1c = 0x0d1c,
+ PK_UNUSED_0d1d = 0x0d1d,
+ PK_UNUSED_0d1e = 0x0d1e,
+ PK_UNUSED_0d1f = 0x0d1f,
+
+ // The following are reserved for instance specific use.
+ // Each engine must define its own XXX_panic_codes.h
+ // Where XXX = SBE, CME, GPE0, GPE1, PGPE, SGPE
+ // They are listed here to show the valid trap values that
+ // can be used.
+
+ //_UNUSED_1c00 = 0x1c00,
+ //_UNUSED_1c01 = 0x1c01,
+ //_UNUSED_1c02 = 0x1c02,
+ //_UNUSED_1c03 = 0x1c03,
+ //_UNUSED_1c04 = 0x1c04,
+ //_UNUSED_1c05 = 0x1c05,
+ //_UNUSED_1c06 = 0x1c06,
+ //_UNUSED_1c07 = 0x1c07,
+ //_UNUSED_1c08 = 0x1c08,
+ //_UNUSED_1c09 = 0x1c09,
+ //_UNUSED_1c0a = 0x1c0a,
+ //_UNUSED_1c0d = 0x1c0d,
+ //_UNUSED_1c1c = 0x1c1c,
+ //_UNUSED_1c1d = 0x1c1d,
+ //_UNUSED_1c1e = 0x1c1e,
+ //_UNUSED_1c1f = 0x1c1f,
+
+ //_UNUSED_1d00 = 0x1d00,
+ //_UNUSED_1d01 = 0x1d01,
+ //_UNUSED_1d02 = 0x1d02,
+ //_UNUSED_1d03 = 0x1d03,
+ //_UNUSED_1d04 = 0x1d04,
+ //_UNUSED_1d05 = 0x1d05,
+ //_UNUSED_1d06 = 0x1d06,
+ //_UNUSED_1d07 = 0x1d07,
+ //_UNUSED_1d08 = 0x1d08,
+ //_UNUSED_1d09 = 0x1d09,
+ //_UNUSED_1d0a = 0x1d0a,
+ //_UNUSED_1d0d = 0x1d0d,
+ //_UNUSED_1d1c = 0x1d1c,
+ //_UNUSED_1d1d = 0x1d1d,
+ //_UNUSED_1d1e = 0x1d1e,
+ //_UNUSED_1d1f = 0x1d1f,
+
+ //_UNUSED_1e00 = 0x1e00,
+ //_UNUSED_1e01 = 0x1e01,
+ //_UNUSED_1e02 = 0x1e02,
+ //_UNUSED_1e03 = 0x1e03,
+ //_UNUSED_1e04 = 0x1e04,
+ //_UNUSED_1e05 = 0x1e05,
+ //_UNUSED_1e06 = 0x1e06,
+ //_UNUSED_1e07 = 0x1e07,
+ //_UNUSED_1e08 = 0x1e08,
+ //_UNUSED_1e09 = 0x1e09,
+ //_UNUSED_1e0a = 0x1e0a,
+ //_UNUSED_1e0d = 0x1e0d,
+ //_UNUSED_1e1c = 0x1e1c,
+ //_UNUSED_1e1d = 0x1e1d,
+ //_UNUSED_1e1e = 0x1e1e,
+ //_UNUSED_1e1f = 0x1e1f,
+
+ //_UNUSED_1f00 = 0x1f00,
+ //_UNUSED_1f01 = 0x1f01,
+ //_UNUSED_1f02 = 0x1f02,
+ //_UNUSED_1f03 = 0x1f03,
+ //_UNUSED_1f04 = 0x1f04,
+ //_UNUSED_1f05 = 0x1f05,
+ //_UNUSED_1f06 = 0x1f06,
+ //_UNUSED_1f07 = 0x1f07,
+ //_UNUSED_1f08 = 0x1f08,
+ //_UNUSED_1f09 = 0x1f09,
+ //_UNUSED_1f0a = 0x1f0a,
+ //_UNUSED_1f0d = 0x1f0d,
+ //_UNUSED_1f1c = 0x1f1c,
+ //_UNUSED_1f1d = 0x1f1d,
+ //_UNUSED_1f1e = 0x1f1e,
+ //_UNUSED_1f1f = 0x1f1f
+} pkPanicCode_t;
+
+#else
+
+/// Assembler specific panic codes
+#define PPE42_MACHINE_CHECK_PANIC 0x0001
+#define PPE42_DATA_STORAGE_PANIC 0x0002
+#define PPE42_INSTRUCTION_STORAGE_PANIC 0x0003
+#define PPE42_DATA_ALIGNMENT_PANIC 0x0004
+
+#define PK_BOOT_VECTORS_NOT_ALIGNED 0x0005
+#define PPE42_ILLEGAL_INSTRUCTION 0x001c
+
+
+
+#endif // __ASSEMBLER__
#endif
diff --git a/import/chips/p9/procedures/ppe/pk/ppe42/ppe42.h b/import/chips/p9/procedures/ppe/pk/ppe42/ppe42.h
index bc747dd4..6857ce10 100644
--- a/import/chips/p9/procedures/ppe/pk/ppe42/ppe42.h
+++ b/import/chips/p9/procedures/ppe/pk/ppe42/ppe42.h
@@ -35,7 +35,7 @@
// Macros to define where declared code is actually compiled
-#ifdef __PPE42_C__
+#ifdef __PPE42_CORE_C__
#define IF__PPE42_CORE_C__(x) x
#define UNLESS__PPE42_CORE_C__(x)
#else
@@ -267,6 +267,7 @@ popcount64(uint64_t x)
#include "ppe42_context.h"
+#include "pk_panic_codes.h"
// PPE42 stack characteristics for PK. The pre-pattern pattern is selected
// to be easily recognizable yet be an illegal instruction.
@@ -283,26 +284,6 @@ popcount64(uint64_t x)
#define PK_THREAD_OFFSET_STACK_LIMIT 4
#define PK_THREAD_OFFSET_STACK_BASE 8
-// PK boot loader panic codes
-
-#define PPE42_BOOT_VECTORS_NOT_ALIGNED 0x00405001
-
-// Interrupt handler panic codes
-
-#define PPE42_DEFAULT_IRQ_HANDLER 0x00405010
-#define PPE42_DEFAULT_SPECIAL_HANDLER 0x00405011
-#define PPE42_PHANTOM_INTERRUPT 0x00405012
-#define PPE42_PROGRAM_HALT 0x00405013
-
-
-// Exception handling invariant panic codes
-
-#define PPE42_IRQ_FULL_EXIT_INVARIANT 0x00405020
-#define PPE42_IRQ_FAST2FULL_INVARIANT 0x00405021
-
-
-// API error panic codes
-
// Application-overrideable definitions
@@ -310,7 +291,7 @@ popcount64(uint64_t x)
/// and all other MSR bits cleared.
///
/// The default definition allows external and machine check exceptions. This
-/// definition can be overriden by the application.
+/// definition can be overriden by the application.
#ifndef PK_THREAD_MACHINE_CONTEXT_DEFAULT
#define PK_THREAD_MACHINE_CONTEXT_DEFAULT \
@@ -321,28 +302,10 @@ popcount64(uint64_t x)
#ifndef __ASSEMBLER__
-/// The PK kernel default panic sequence for C code
-///
-/// By default a kernel panic from C code forces external debug mode then
-/// generates a \c trap instruction followed by the error code. The \a code
-/// argument must be a compile-time integer immediate. This definition can be
-/// overriden by the application.
-///
-/// The OCC may be running in internal debug mode for various reasons, and
-/// TRAP-ing in internal debug mode would lead to an infinite loop in the
-/// default Program Interrupt handler - which itself would be a TRAP (since
-/// that's the default implementation of PK_PANIC(). Therefore by default
-/// the panic is implemented as a special code sequence that forces the core
-/// into external debug mode before issuing a TRAP which will halt the core.
-/// To preserve the state we use the special global variables
-/// __pk_panic_save_dbcr0 and __pk_panic_save_r3 defined in ppe42_core.c.
-/// The original value of DBCR0 is destroyed, but can be recovered from the
-/// global. In the end %r3 is reloaded from temporary storage and will be
-/// unchanged at the halt.
+/// The PK kernel default panic sequence for C code is to issue a trap
+/// instruction with DBCR[TRAP] set, which causes XSR[TRAP] <- 1
+/// and causes the PPE to halt.
///
-/// Note that there is a small chance that an interrupt will fire and
-/// interrupt this code before the halt - in general there is no way around
-/// this.
///
/// The Simics environment does not model Debug events correctly. It executes
/// the TRAP as an illegal instruction and branches to the Program Interrupt
@@ -351,39 +314,41 @@ popcount64(uint64_t x)
/// before the hardware trap. The special-form magic instruction is
/// recognized by our Simics support scripts which decode the kernel state and
/// try to help the user interpret what happened based on the TRAP code.
+/// NOTE! SIMICS does not seem to recognize the "magic breakpoint" on PPE!
+
#ifndef PK_PANIC
-/*#define PK_PANIC(code) \
- do { \
- barrier(); \
- asm volatile ("stw %r3, __pk_panic_save_r3@sda21(0)"); \
- asm volatile ("mfdbcr0 %r3"); \
- asm volatile ("stw %r3, __pk_panic_save_dbcr0@sda21(0)"); \
- asm volatile ("lwz %r3, __pk_panic_dbcr0@sda21(0)"); \
- asm volatile ("mtdbcr0 %r3"); \
- asm volatile ("isync"); \
- asm volatile ("lwz %r3, __pk_panic_save_r3@sda21(0)"); \
- asm volatile ("rlwimi 1,1,0,0,0"); \
- asm volatile ("trap"); \
+#if SIMICS_ENVIRONMENT
+#define PK_PANIC(code) \
+ do { \
+ asm volatile ("stw %r3, __pk_panic_save_r3@sda21(0)"); \
+ asm volatile ("lwz %r3, __pk_panic_dbcr@sda21(0)"); \
+ asm volatile ("mtdbcr %r3"); \
asm volatile (".long %0" : : "i" (code)); \
- } while (0)
-*/
-#define PK_PANIC(code) \
+ } while(0)
+#else
+#define PK_PANIC(code) \
do { \
- barrier(); \
- asm volatile ("b ."); \
+ asm volatile ("tw 31, %0, %1" : : "i" (code/256) , "i" (code%256)); \
} while (0)
+#endif
+#endif // SIMICS_ENVIRONMENT
// These variables are used by the PK_PANIC() definition above to save and
-// restore state. __pk_panic_dbcr0 is the value loaded into DBCR0 to force
-// traps to halt the OCC and freeze the timers.
-
-//#ifdef __PPE42_CORE_C__
-//uint32_t __pk_panic_save_r3;
-//uint32_t __pk_panic_save_dbcr0;
-//uint32_t __pk_panic_dbcr0 = DBCR0_EDM | DBCR0_TDE | DBCR0_FT;
-//#endif
+// restore state. __pk_panic_dbcr is the value loaded into DBCR to force
+// traps to halt the PPE and freeze the timers.
+
+#if SIMICS_ENVIRONMENT
+#ifdef __PPE42_CORE_C__
+uint32_t __pk_panic_save_r3;
+uint32_t __pk_panic_dbcr = DBCR_RST_HALT;
+#define __PK_PANIC_DEFS__
+#else
+#define __PK_PANIC_DEFS__ \
+ extern uint32_t __pk_panic_save_r3; \
+ extern uint32_t __pk_panic_dbcr;
+#endif //SIMICS_ENVIRONMENT
#endif // PK_PANIC
@@ -396,7 +361,7 @@ popcount64(uint64_t x)
//#define SIMICS_MAGIC_BREAKPOINT asm volatile ("rlwimi 0,0,0,0,0")
/// This is the Simics 'magic breakpoint' instruction including a memory
-/// barrier.
+/// barrier.
///
/// Note that the memory barrier guarantees that all variables held in
/// registers are flushed to memory before the breakpoint, however this might
@@ -436,11 +401,18 @@ popcount64(uint64_t x)
#ifndef PK_PANIC
#define PK_PANIC(code) _pk_panic code
-
+#if SIMICS_ENVIRONMENT
+ .macro _pk_panic, code
+ stw %r3, __pk_panic_save_r3@sda21(0)
+ lwz %r3, __pk_panic_dbcr@sda21(0)
+ mtdbcr %r3,
+ .long (\code)
+ .endm
+#else
.macro _pk_panic, code
- b .
+ tw 31,(\code)/256, (\code)%256
.endm
-
+#endif // SIMICS_ENVIRONMENT
#endif // PK_PANIC
// *INDENT-ON*
@@ -504,7 +476,7 @@ popcount64(uint64_t x)
typedef uint32_t PkMachineContext;
/// Disable interrupts and return the current
-/// context.
+/// context.
///
/// \param context A pointer to an PkMachineContext, this is the context that
/// existed before interrupts were disabled. Typically this
@@ -535,7 +507,7 @@ return PK_OK;
///
/// \retval 0 Successful completion
///
-/// \retval -PK_INVALID_ARGUMENT_CONTEXT_SET A null pointer was provided as
+/// \retval -PK_INVALID_ARGUMENT_CONTEXT_SET A null pointer was provided as
/// the \a context argument or an illegal machine context was specified.
UNLESS__PPE42_CORE_C__(extern)
@@ -560,7 +532,7 @@ return PK_OK;
///
/// \retval 0 Successful completion
///
-/// \retval -PK_INVALID_ARGUMENT_CONTEXT_GET A null pointer was provided as
+/// \retval -PK_INVALID_ARGUMENT_CONTEXT_GET A null pointer was provided as
/// the \a context argument.
UNLESS__PPE42_CORE_C__(extern)
@@ -579,7 +551,7 @@ return PK_OK;
extern void __ctx_switch();
/// The PK context switch for the PPE kernel
-// There is no protected mode in PPE42 so just call kernel code
+// There is no protected mode in PPE42 so just call kernel code
#define __pk_switch() __ctx_switch()
@@ -588,14 +560,14 @@ extern void __ctx_switch();
/// behind the SP are for the initial subroutine's LR.
static inline void
-__pk_stack_create_initial_frame(PkAddress* stack, size_t* size) \
+__pk_stack_create_initial_frame(PkAddress* stack, size_t* size)
{
*stack -= 8;
* size -= 8;
* ((PK_STACK_TYPE*)(*stack)) = 0;
}
-/// The PK Kernel Context for PPE42
+/// The PK Kernel Context for PPE42
///
/// The PK portable kernel does not define how the kernel keeps track of
/// whether PK is running, interrupt levels, and other debug
@@ -614,7 +586,7 @@ struct
{
/// A flag indicating that PK is in thread mode after a call of
-/// pk_start_threads().
+/// pk_start_threads().
unsigned thread_mode : 1;
/// If this field is non-zero then PK is processing an interrupt
@@ -710,10 +682,10 @@ mtmsr(mctx);
// queue).
//
// These queues are used both for the run queue and the pending queue
-// associated with every semaphore.
+// associated with every semaphore.
//
// On PPE42 with 32 threads (implied), this is a job for a uint32_t and
-// cntlzw().
+// cntlzw().
static inline void
__pk_thread_queue_clear(volatile PkThreadQueue* queue)
@@ -809,13 +781,13 @@ return __builtin_popcount(*queue);
/// Once hit, restarting from the break requires clearing IAC4 and restarting
/// instructions:
///
-/// \code
+/// \code
///
/// putspr pu.occ iac4 0
/// cipinstruct pu.occ start
///
/// \endcode
-///
+///
/// The above restart processes is also encapsulated as the p8_tclEcmd
/// procedure 'unbreakOcc'.
///
diff --git a/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_boot.S b/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_boot.S
index f51b1c2a..6c3424f5 100644
--- a/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_boot.S
+++ b/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_boot.S
@@ -133,7 +133,7 @@ __reset_trap:
#_liw %r3, __vectors
#andi. %r4, %r3, 0x01ff
#beq 1f
- #_pk_panic PPE42_BOOT_VECTORS_NOT_ALIGNED
+ #_pk_panic PK_BOOT_VECTORS_NOT_ALIGNED
#1:
#mtivpr %r3
#sync
diff --git a/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_irq.h b/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_irq.h
index f6f1964a..24f30fa1 100644
--- a/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_irq.h
+++ b/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_irq.h
@@ -59,19 +59,20 @@
// would most likely be a branch to an application-defined handler.
#ifndef PPE42_MACHINE_CHECK_HANDLER
- #define PPE42_MACHINE_CHECK_HANDLER PK_PANIC(0x0200)
+ #define PPE42_MACHINE_CHECK_HANDLER PK_PANIC( PPE42_MACHINE_CHECK_PANIC)
#endif
#ifndef PPE42_DATA_STORAGE_HANDLER
- #define PPE42_DATA_STORAGE_HANDLER PK_PANIC(0x0300)
+ #define PPE42_DATA_STORAGE_HANDLER PK_PANIC(PPE42_DATA_STORAGE_PANIC)
#endif
#ifndef PPE42_INSTRUCTION_STORAGE_HANDLER
- #define PPE42_INSTRUCTION_STORAGE_HANDLER PK_PANIC(0x0400)
+#define PPE42_INSTRUCTION_STORAGE_HANDLER \
+ PK_PANIC(PPE42_INSTRUCTION_STORAGE_PANIC)
#endif
#ifndef PPE42_ALIGNMENT_HANDLER
- #define PPE42_ALIGNMENT_HANDLER PK_PANIC(0x0600)
+ #define PPE42_ALIGNMENT_HANDLER PK_PANIC(PPE42_DATA_ALIGNMENT_PANIC)
#endif
diff --git a/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_irq_core.c b/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_irq_core.c
index 7e369a02..0021457f 100644
--- a/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_irq_core.c
+++ b/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_irq_core.c
@@ -51,7 +51,7 @@
void
__ppe42_default_irq_handler(void* arg, PkIrqId irq)
{
- PK_PANIC(PPE42_DEFAULT_IRQ_HANDLER);
+ PK_PANIC(PK_DEFAULT_IRQ_HANDLER);
}
diff --git a/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_spr.h b/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_spr.h
index 82fed011..f95139bd 100644
--- a/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_spr.h
+++ b/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_spr.h
@@ -63,10 +63,14 @@
/* DBCR - Debug Control Register */
-#define DBCR_RST 0x30000000 /* Reset: 01=Soft Reset, 10=Hard Reset, 11=Halt */
+#define DBCR_RST_SOFT 0x10000000 /* Reset: 01=Soft Reset */
+#define DBCR_RST_HARD 0x20000000 /* Reset: 10=Hard Reset */
+#define DBCR_RST_HALT 0x30000000 /* Reset: 11=Halt */
#define DBCR_TRAP 0x01000000 /* Trap Instruction Enable */
#define DBCR_IACE 0x00800000 /* Instruction Address Compare Enable */
-#define DBCR_DACE 0x000c0000 /* Data Address Compare Enable: 01=store, 10=load, 11=both */
+#define DBCR_DACE_ST 0x00040000 /* Data Address Compare Enable: 01=store */
+#define DBCR_DACE_LD 0x00080000 /* Data Address Compare Enable: 10=load */
+#define DBCR_DACE_STLD 0x000C0000 /* Data Address Compare Enable: 11=both */
/* TCR - Timer Control Register */
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