Ec_level attribute support for DD1 attributes

--Fixig hb_temp_defaults.xml

Change-Id: Iab140154483b10bd05a6dba092dad25f64eae742
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/26450
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Andrew J. Geissler <andrewg@us.ibm.com>
Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/26487
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>

7 files changed, 99 insertions, 55 deletions

diff --git a/import/chips/p9/procedures/hwp/perv/p9_sbe_arrayinit.C b/import/chips/p9/procedures/hwp/perv/p9_sbe_arrayinit.C
index 4ee98c25..8f6e2d0c 100644
--- a/import/chips/p9/procedures/hwp/perv/p9_sbe_arrayinit.C
+++ b/import/chips/p9/procedures/hwp/perv/p9_sbe_arrayinit.C
@@ -67,7 +67,7 @@ fapi2::ReturnCode p9_sbe_arrayinit(const
     fapi2::buffer<uint8_t> l_attr_read;
     FAPI_INF("Entering ...");
 
-    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SDISN_SETUP, i_target_chip, l_attr_read));
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_SDISN_SETUP, i_target_chip, l_attr_read));
 
     for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
          (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_MC |
diff --git a/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C b/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C
index 75173853..19019e71 100644
--- a/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C
+++ b/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C
@@ -139,7 +139,7 @@ fapi2::ReturnCode p9_sbe_chiplet_reset(const
     fapi2::TargetState l_target_state = fapi2::TARGET_STATE_FUNCTIONAL;
     FAPI_INF("Entering ...");
 
-    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_VITL_CLK_SETUP, i_target_chip,
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_VITL_CLK_SETUP, i_target_chip,
                            l_attr_vitl_setup));
 
     for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
diff --git a/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_startclocks.C b/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_startclocks.C
index afc9ae77..34f6619a 100644
--- a/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_startclocks.C
+++ b/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_startclocks.C
@@ -81,7 +81,7 @@ fapi2::ReturnCode p9_sbe_nest_startclocks(const
     fapi2::buffer<uint16_t> l_n3_ccstatus_regions;
     FAPI_INF("Entering ...");
 
-    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_N3_FLUSH_MODE, i_target_chip,
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_N3_FLUSH_MODE, i_target_chip,
                            l_read_flush_attr));
 
     for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
diff --git a/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_arrayinit.C b/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_arrayinit.C
index 97120c32..0f35e474 100644
--- a/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_arrayinit.C
+++ b/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_arrayinit.C
@@ -66,7 +66,7 @@ fapi2::ReturnCode p9_sbe_tp_arrayinit(const
 
     FAPI_INF("Entering ...");
 
-    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SDISN_SETUP, i_target_chip, l_attr_read));
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_SDISN_SETUP, i_target_chip, l_attr_read));
 
     FAPI_DBG("Exclude PIBMEM from TP array init");
     //Setting PIBMEM_REPAIR_REGISTER_0 register value
diff --git a/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
index b56d4cea..72918cce 100644
--- a/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
+++ b/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
@@ -85,4 +85,77 @@
       </chip>
     </chipEcFeature>
   </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_VITL_CLK_SETUP</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Nimbus DD1 for differentiating present/functional targets. True if:
+      Nimbus EC less than 20
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_NIMBUS</name>
+        <ec>
+          <value>0x20</value>
+          <test>LESS_THAN</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+  <!-- ******************************************************************** -->
+  <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_FSI_GP_SHADOWS_OVERWRITE</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      DD1 attribute for assigning flushvalues to root_ctrl and perv_ctrl registers. True if:
+      Nimbus EC less than 20
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_NIMBUS</name>
+        <ec>
+          <value>0x20</value>
+          <test>LESS_THAN</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+  <!-- ******************************************************************** -->
+  <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_N3_FLUSH_MODE</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      DD1 update : Flush mode not initiated for N3. True if:
+      Nimbus EC less than 20
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_NIMBUS</name>
+        <ec>
+          <value>0x20</value>
+          <test>LESS_THAN</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+  <!-- ******************************************************************** -->
+  <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_SDISN_SETUP</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Sdis_n set or clear : flushing LCBES condition woraround. True if:
+      Nimbus EC less than 20
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_NIMBUS</name>
+        <ec>
+          <value>0x20</value>
+          <test>LESS_THAN</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+  <!-- ******************************************************************** -->
 </attributes>
diff --git a/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml b/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml
index 9bdc0209..22512606 100644
--- a/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml
+++ b/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml
@@ -586,10 +586,6 @@
   	<value>0x00000FFF</value>
   </entry>
   <entry>
-           <name>ATTR_SDISN_SETUP</name>
-           <value>0x1</value>
-  </entry>
-  <entry>
            <name>ATTR_SECURITY_MODE</name>
            <value>0x0</value>
   </entry>
@@ -600,31 +596,32 @@
            <name>ATTR_PFET_OFF_CONTROLS</name>
   </entry>
   <entry>
-           <name>ATTR_N3_FLUSH_MODE</name>
-           <value>0x1</value>
+           <name>ATTR_OBUS_RATIO_VALUE</name>
   </entry>
   <entry>
-           <name>ATTR_VITL_CLK_SETUP</name>
-           <value>0x1</value>
+           <name>ATTR_ECID</name>
   </entry>
   <entry>
-           <name>ATTR_OBUS_RATIO_VALUE</name>
+           <name>ATTR_RUNN_MODE</name>
+           <value>0x0</value>
   </entry>
   <entry>
-           <name>ATTR_FSI_GP_SHADOWS_OVERWRITE</name>
+           <name>ATTR_SS_FILTER_BYPASS</name>
+           <value>0x0</value>
   </entry>
   <entry>
-           <name>ATTR_ECID</name>
+           <name>ATTR_CP_FILTER_BYPASS</name>
+           <value>0x0</value>
   </entry>
   <entry>
-           <name>ATTR_RUNN_MODE</name>
+           <name>ATTR_IO_FILTER_BYPASS</name>
            <value>0x0</value>
   </entry>
    <!-- See chip_attributes.xml for a description of ATTR_EC -->
   <entry>
            <name>ATTR_EC</name>
            <!-- The value needs to be changed as per the EC level  -->
-           <value>0x00</value>
+           <value>0x10</value>
   </entry>
   <!-- See chip_attributes.xml for a description of ATTR_NAME -->
   <entry>
@@ -641,16 +638,22 @@ attribute tank
            <virtual/>
   </entry>
 -->
+
+<!-- Pervasive EC attributes -->
   <entry>
-           <name>ATTR_SS_FILTER_BYPASS</name>
-           <value>0x0</value>
+           <name>ATTR_CHIP_EC_FEATURE_FSI_GP_SHADOWS_OVERWRITE</name>
+           <virtual/>
   </entry>
   <entry>
-           <name>ATTR_CP_FILTER_BYPASS</name>
-           <value>0x0</value>
+           <name>ATTR_CHIP_EC_FEATURE_N3_FLUSH_MODE</name>
+           <virtual/>
   </entry>
   <entry>
-           <name>ATTR_IO_FILTER_BYPASS</name>
-           <value>0x0</value>
+           <name>ATTR_CHIP_EC_FEATURE_VITL_CLK_SETUP</name>
+            <virtual/>
+  </entry>
+  <entry>
+           <name>ATTR_CHIP_EC_FEATURE_SDISN_SETUP</name>
+           <virtual/>
   </entry>
 </entries>
diff --git a/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml b/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml
index f2e4c67d..2ea17c6d 100644
--- a/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml
+++ b/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml
@@ -553,14 +553,6 @@
 </attribute>
 
 <attribute>
-  <id>ATTR_SDISN_SETUP</id>
-  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
-  <description>Sdis_n set or clear : flushing LCBES condition woraround</description>
-  <valueType>uint8</valueType>
-  <platInit/>
-</attribute>
-
-<attribute>
   <id>ATTR_SECURITY_ENABLE</id>
   <targetType>TARGET_TYPE_SYSTEM</targetType>
   <description>Holds the state of Security Access Bit (SAB)</description>
@@ -588,14 +580,6 @@
 </attribute>
 
 <attribute>
-    <id>ATTR_VITL_CLK_SETUP</id>
-    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
-    <description>Nimbus DD1</description>
-    <valueType>uint8</valueType>
-    <platInit/>    
-</attribute>
-
-<attribute>
     <id>ATTR_OBUS_RATIO_VALUE</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>Holds Obus ratio value</description>
@@ -642,22 +626,6 @@
 </attribute>
 
 <attribute>
-    <id>ATTR_FSI_GP_SHADOWS_OVERWRITE</id>
-    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
-    <description>DD1 attribute for assigning flushvalues to root_ctrl and perv_ctrl registers</description>
-    <valueType>uint8</valueType>
-    <platInit/>
-</attribute>
-
-<attribute>
-    <id>ATTR_N3_FLUSH_MODE</id>
-    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
-    <description>DD1 update : Flush mode not for N3</description>
-    <valueType>uint8</valueType>
-    <platInit/>
-</attribute>
-
-<attribute>
     <id>ATTR_CP_FILTER_BYPASS</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>To skip the locking sequence and check for lock of CP PLL</description>