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authorNick Klazynski <jklazyns@us.ibm.com>2017-11-02 15:34:08 -0500
committerSachin Gupta <sgupta2m@in.ibm.com>2017-11-13 11:42:22 -0500
commitf3e9580127e0bc7c91968484ce6e615878689c02 (patch)
tree40d03d882cd7ef19f187bf35bd516af2e76f47d2
parenta99727e54d98ae1db3a9ef8ad0d071af9200e22f (diff)
downloadtalos-sbe-f3e9580127e0bc7c91968484ce6e615878689c02.tar.gz
talos-sbe-f3e9580127e0bc7c91968484ce6e615878689c02.zip
HW403465 applies to all chips; Revert NDD2.1 RL; add SW406970
Per Ron Kalla's request, NDD2.1 should not use risklevel Change-Id: I2354c2523d760ac16f7c4c2429003ef07e58225d CQ: HW403465 CQ: SW406970 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49148 Dev-Ready: James N. Klazynski <jklazyns@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: James N. Klazynski <jklazyns@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49152 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
-rw-r--r--src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml51
1 files changed, 28 insertions, 23 deletions
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
index 1373bc75..a558846e 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
@@ -724,6 +724,30 @@
</attribute>
<!-- ******************************************************************** -->
<attribute>
+ <id>ATTR_CHIP_EC_FEATURE_SW406970</id>
+ <targetType>TARGET_TYPE_PROC_CHIP, TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+ SW406970 - SCOM clockgating issue
+ </description>
+ <chipEcFeature>
+ <chip>
+ <name>ENUM_ATTR_NAME_NIMBUS</name>
+ <ec>
+ <value>0x22</value>
+ <test>LESS_THAN_OR_EQUAL</test>
+ </ec>
+ </chip>
+ <chip>
+ <name>ENUM_ATTR_NAME_CUMULUS</name>
+ <ec>
+ <value>0x10</value>
+ <test>EQUAL</test>
+ </ec>
+ </chip>
+ </chipEcFeature>
+ </attribute>
+ <!-- ******************************************************************** -->
+ <attribute>
<id>ATTR_CHIP_EC_FEATURE_HW362088</id>
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
<description>
@@ -2643,25 +2667,6 @@
</attribute>
<!-- ******************************************************************** -->
<attribute>
- <id>ATTR_CHIP_EC_FEATURE_HW403465</id>>
- <targetType>TARGET_TYPE_PROC_CHIP</targetType>
- <description>
- Nimbus DD1.0 DD2.0
- L1 access latency increases when data footprint should still
- be within L1 cache size. Revert L1 LRU changes
- </description>
- <chipEcFeature>
- <chip>
- <name>ENUM_ATTR_NAME_NIMBUS</name>
- <ec>
- <value>0x20</value>
- <test>LESS_THAN_OR_EQUAL</test>
- </ec>
- </chip>
- </chipEcFeature>
- </attribute>
- <!-- ******************************************************************** -->
- <attribute>
<id>ATTR_CHIP_EC_FEATURE_HW402145</id>>
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
<description>
@@ -3885,21 +3890,21 @@
<id>ATTR_CHIP_EC_FEATURE_HW417829</id>
<targetType>TARGET_TYPE_PROC_CHIP, TARGET_TYPE_PROC_CHIP</targetType>
<description>
- HW417829 - Bad rfscv branch
+ HW417829 / HW423787 - Bad rfscv branch
</description>
<chipEcFeature>
<chip>
<name>ENUM_ATTR_NAME_NIMBUS</name>
<ec>
- <value>0x20</value>
- <test>GREATER_THAN_OR_EQUAL</test>
+ <value>0x21</value>
+ <test>LESS_THAN_OR_EQUAL</test>
</ec>
</chip>
<chip>
<name>ENUM_ATTR_NAME_CUMULUS</name>
<ec>
<value>0x10</value>
- <test>GREATER_THAN_OR_EQUAL</test>
+ <test>EQUAL</test>
</ec>
</chip>
</chipEcFeature>
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