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| author | Greg Still <stillgs@us.ibm.com> | 2018-09-26 12:40:03 -0500 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2018-10-05 20:44:08 -0500 |
| commit | e4bd0e56146bed5ce7d00fb3225ac06d3cb0048c (patch) | |
| tree | ee9cd42eed00cdb268f4747ebce17615499a070a | |
| parent | 6ef77d03b31f971caa3be474e101c132351977d1 (diff) | |
| download | talos-sbe-e4bd0e56146bed5ce7d00fb3225ac06d3cb0048c.tar.gz talos-sbe-e4bd0e56146bed5ce7d00fb3225ac06d3cb0048c.zip | |
SMF: clear HRMOR[15] in all modes so that secure mode won't hang core
Key_Cronus_Test=PM_REGRESS
Change-Id: I26a98dfce1eb8123c79b35f2f4dc1783e16e411e
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/66687
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Dev-Ready: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com>
Reviewed-by: YUE DU <daviddu@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/66693
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C index 83b5cbc9..e942d319 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C @@ -257,11 +257,6 @@ ram_sprs( l_ram_data -= l_bootloader_offset; } - // set HRMOR -- core level SPR - FAPI_TRY(fapi2::putScom(l_master_core_target , P9N2_C_HRMOR, l_ram_data ), - "Error Writing To HRMOR"); - FAPI_DBG("Wrote HRMOR with 0x%016lX", (uint64_t)l_ram_data); - // get MSR to determine if need to set URMOR FAPI_TRY(l_ram_t2.get_reg(REG_SPR, MSR_SPR_NUMBER, &l_msr), "Error ramming MSR (T2)!"); @@ -274,6 +269,13 @@ ram_sprs( FAPI_DBG("Wrote URMOR with 0x%016lX", (uint64_t)l_ram_data ); } + // set HRMOR -- core level SPR + // Must not set bit 15 in HRMOR. Only applies to URMOR. + l_ram_data.clearBit<15>(); + FAPI_TRY(fapi2::putScom(l_master_core_target , P9N2_C_HRMOR, l_ram_data ), + "Error Writing To HRMOR"); + FAPI_DBG("Wrote HRMOR with 0x%016lX", (uint64_t)l_ram_data); + // set PSSCR via thread specific instances l_ram_data = HOSTBOOT_PSSCR_VALUE; FAPI_DBG("PSSCR with 0x%16llX", (uint64_t)l_ram_data); |
