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author | Joe McGill <jmcgill@us.ibm.com> | 2017-04-07 08:16:05 -0500 |
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committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2017-04-13 00:28:38 -0400 |
commit | dc47a092f6faa2cb838f0bcd046bce3cab50aa65 (patch) | |
tree | c167655eab269b422ccc0e57d03f6e375c6b718b | |
parent | 1e8dfdb101ec6ceb85c6f9a1d7c9a076d0569b75 (diff) | |
download | talos-sbe-dc47a092f6faa2cb838f0bcd046bce3cab50aa65.tar.gz talos-sbe-dc47a092f6faa2cb838f0bcd046bce3cab50aa65.zip |
p9_htm_setup -- cleanup start behavior for multi-chip systems
Current code will generate an error (not propogated back to caller)
when attempting to start HTM on p1 via ADU. ADU sequence on p1 fails
based on attempting to interlock PB token manager quiesce on slave
fabric chip
A platform change is also required here to get the correct start
behavior. The i_start parameter should be set to true only for
the 'last' chip to be initialized in this istep -- this will ensure
all chips are properly configured, and the last invocation will
trigger all HTMs to begin execution.
p9_adu_coherent_utils
Issue global HTM start (pmisc) without quiesce + reinit sequence
via ADU OPTION reg. Remove TM quiesce interlock as well
p9_htm_adu_ctrl
Rework return code propogation to correctly return first error
Change-Id: Iabac85e4e0341894809464b2d206483170b79f00
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38981
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: CHRISTINA L. GRAVES <clgraves@us.ibm.com>
Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38983
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
-rw-r--r-- | src/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.C | 18 |
1 files changed, 10 insertions, 8 deletions
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.C b/src/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.C index a9af9369..8c421d98 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.C @@ -484,12 +484,6 @@ extern "C" // Set AXTYPE = Address only altd_cmd_reg_data.setBit<ALTD_CMD_ADDRESS_ONLY_BIT>(); - // Set OVERWRITE_PBINIT - altd_cmd_reg_data.setBit<ALTD_CMD_OVERWRITE_PBINIT_BIT>(); - - // Set TM_QUIESCE - altd_cmd_reg_data.setBit<ALTD_CMD_WITH_TM_QUIESCE_BIT>(); - // --------------------------------------------------- // PB specific: TTYPE & TSIZE // --------------------------------------------------- @@ -501,6 +495,8 @@ extern "C" // Set TTYPE altd_cmd_reg_data.insertFromRight<ALTD_CMD_TTYPE_START_BIT, ALTD_CMD_TTYPE_NUM_BITS>(ALTD_CMD_TTYPE_PB_OPER); + // Set TM_QUIESCE + altd_cmd_reg_data.setBit<ALTD_CMD_WITH_TM_QUIESCE_BIT>(); if (l_operType == p9_ADU_oper_flag::PB_DIS_OPER) { @@ -510,6 +506,9 @@ extern "C" } else { + // Set OVERWRITE_PBINIT + altd_cmd_reg_data.setBit<ALTD_CMD_OVERWRITE_PBINIT_BIT>(); + // Set up quiesce altd_option_reg_data.setBit<FBC_ALTD_WITH_PRE_QUIESCE>(); altd_option_reg_data.insertFromRight<FBC_ALTD_PRE_QUIESCE_COUNT_START_BIT, @@ -538,8 +537,13 @@ extern "C" // Set TSIZE if ( l_transSize == p9_ADU_oper_flag::TSIZE_1 ) { + // Set TM_QUIESCE + altd_cmd_reg_data.setBit<ALTD_CMD_WITH_TM_QUIESCE_BIT>(); + altd_cmd_reg_data.insertFromRight<ALTD_CMD_TSIZE_START_BIT, ALTD_CMD_TSIZE_NUM_BITS>(ALTD_CMD_PMISC_TSIZE_1); + // Set quiesce and init around a switch operation in option reg + FAPI_TRY(setQuiesceInit(i_target), "setQuiesceInit() returns error"); } else if ( l_transSize == p9_ADU_oper_flag::TSIZE_2 ) { @@ -547,8 +551,6 @@ extern "C" ALTD_CMD_TSIZE_NUM_BITS>(ALTD_CMD_PMISC_TSIZE_2); } - // Set quiesce and init around a switch operation in option reg - FAPI_TRY(setQuiesceInit(i_target), "setQuiesceInit() returns error"); } } |