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authorRaja Das <rajadas2@in.ibm.com>2017-06-05 08:39:39 -0500
committerSachin Gupta <sgupta2m@in.ibm.com>2017-06-05 23:15:34 -0400
commitd1f28c84ae9515ecf65db67f124edb35771c893f (patch)
tree6bd13c97646265ca36cd3dc010f45a5cbed2dde4
parent4e9be1ee9a6ea96f7d44314156f9e989ba03b914 (diff)
downloadtalos-sbe-d1f28c84ae9515ecf65db67f124edb35771c893f.tar.gz
talos-sbe-d1f28c84ae9515ecf65db67f124edb35771c893f.zip
Added traces to figure out the infinite loop in the mpipl path
Change-Id: Iabe0a1ae22e0a18915a3ca645932e09b3bf83b28 CQ: SW386997 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41361 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41365 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
-rw-r--r--src/import/chips/p9/procedures/hwp/nest/p9_sbe_check_quiesce.C16
-rw-r--r--src/import/chips/p9/procedures/hwp/perv/p9_sbe_sequence_drtm.C9
-rw-r--r--src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_indir_access.C4
3 files changed, 24 insertions, 5 deletions
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_check_quiesce.C b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_check_quiesce.C
index dbcc2e6e..6cc1f91a 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_check_quiesce.C
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_check_quiesce.C
@@ -82,6 +82,7 @@ extern "C" {
fapi2::ReturnCode p9_sbe_check_quiesce(const
fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
{
+ FAPI_IMP("p9_sbe_check_quiesce: Entering..");
// mark HWP entry
// SBE will check quiesce state for all units on the powerbus on its chip
@@ -110,6 +111,7 @@ extern "C" {
}
}
+ FAPI_IMP("p9_sbe_check_quiesce: Exiting..");
return saveError;
}
@@ -122,6 +124,7 @@ extern "C" {
//---------------------------------------------------------------------------------
fapi2::ReturnCode p9_capp_check_quiesce(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
{
+ FAPI_IMP("p9_capp_check_quiesce: Entering ....");
// mark HWP entry
fapi2::buffer<uint64_t> l_data(0);
@@ -207,6 +210,7 @@ extern "C" {
}
fapi_try_exit:
+ FAPI_IMP("p9_capp_check_quiesce: Exiting ....");
return fapi2::current_err;
}
@@ -215,6 +219,7 @@ extern "C" {
//---------------------------------------------------------------------------------
fapi2::ReturnCode p9_phb_check_quiesce(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
{
+ FAPI_IMP("p9_phb_check_quiesce: Entering ...");
// mark HWP entry
fapi2::buffer<uint64_t> l_data(0);
//We want to set bit 0 (the Quiesce DMA bit)
@@ -289,6 +294,7 @@ extern "C" {
FAPI_TRY(p9_suspend_io(i_target, true), "ERROR suspending IO");
fapi_try_exit:
+ FAPI_IMP("p9_phb_check_quiesce: Exiting ...");
return fapi2::current_err;
}
@@ -297,6 +303,7 @@ extern "C" {
//---------------------------------------------------------------------------------
fapi2::ReturnCode p9_npu_check_quiesce(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
{
+ FAPI_IMP("p9_npu_check_quiesce: Entering...");
// mark HWP entry
const uint32_t c_fence_status_reg_size = 6;
@@ -415,6 +422,7 @@ extern "C" {
}
fapi_try_exit:
+ FAPI_IMP("p9_npu_check_quiesce: Exiting...");
return fapi2::current_err;
}
@@ -423,6 +431,7 @@ extern "C" {
//---------------------------------------------------------------------------------
fapi2::ReturnCode p9_vas_check_quiesce(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
{
+ FAPI_IMP("p9_vas_check_quiesce: Entering...");
// mark HWP entry
fapi2::buffer<uint64_t> l_vas_north_misc_ctl_data(0);
@@ -472,6 +481,7 @@ extern "C" {
fapi2::putScom(i_target, PU_VAS_MISCCTL, l_vas_north_misc_ctl_data);
fapi_try_exit:
+ FAPI_IMP("p9_vas_check_quiesce: Exiting...");
return fapi2::current_err;
}
@@ -480,6 +490,7 @@ extern "C" {
//---------------------------------------------------------------------------------
fapi2::ReturnCode p9_nx_check_quiesce(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
{
+ FAPI_IMP("p9_nx_check_quiesce: Entering....");
// mark HWP entry
fapi2::buffer<uint64_t> l_dma_status_reg_data(0);
@@ -671,6 +682,7 @@ extern "C" {
#endif
fapi_try_exit:
+ FAPI_IMP("p9_nx_check_quiesce: Exiting....");
return fapi2::current_err;
}
@@ -679,6 +691,7 @@ extern "C" {
//---------------------------------------------------------------------------------
fapi2::ReturnCode p9_psihb_check_quiesce(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
{
+ FAPI_IMP("p9_psihb_check_quiesce: Entering...");
// mark HWP entry
fapi2::buffer<uint64_t> l_psihb_data(0);
@@ -719,6 +732,7 @@ extern "C" {
fapi2::putScom(i_target, PU_TRUST_CONTROL, l_psihb_data);
fapi_try_exit:
+ FAPI_IMP("p9_psihb_check_quiesce: Exiting...");
return fapi2::current_err;
}
@@ -727,6 +741,7 @@ extern "C" {
//---------------------------------------------------------------------------------
fapi2::ReturnCode p9_intp_check_quiesce(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
{
+ FAPI_IMP("p9_intp_check_quiesce: Entering...");
// mark HWP entry
fapi2::buffer<uint64_t> l_data(0);
@@ -886,6 +901,7 @@ extern "C" {
#endif
fapi_try_exit:
+ FAPI_IMP("p9_intp_check_quiesce: Exiting...");
return fapi2::current_err;
}
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_sequence_drtm.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_sequence_drtm.C
index c8bcf970..14bab3e9 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_sequence_drtm.C
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_sequence_drtm.C
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER sbe Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2016 */
+/* Contributors Listed Below - COPYRIGHT 2016,2017 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -158,14 +158,17 @@ fapi2::ReturnCode p9_sbe_sequence_drtm(const fapi2::Target<fapi2::TARGET_TYPE_PR
FAPI_DBG("Current Chip on the system not quiesced - %#018lx", (uint64_t(1) << (63 - validchip)));
break; //From while loop with PENDING return code
}
-
+ else
+ {
+ FAPI_IMP("Chip [%#018lx] has LQA set", (uint64_t(1) << (63 - validchip)));
+ FAPI_IMP("Current System configuration : %#010lx - %#x", (l_sys_config >> 32), (uint32_t)l_sys_config);
+ }
}
validchip++;
} //End of while (validchip <= 63)
-
FAPI_INF("p9_sbe_sequence_drtm : Exiting ...");
fapi_try_exit:
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_indir_access.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_indir_access.C
index bae4958a..15161f84 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_indir_access.C
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_indir_access.C
@@ -74,7 +74,7 @@ fapi2::ReturnCode p9_pm_ocb_indir_access(
uint32_t& o_ocb_act_length,
uint64_t* io_ocb_buffer)
{
- FAPI_IMP("Enter p9_pm_ocb_indir_access...");
+ FAPI_DBG("Enter p9_pm_ocb_indir_access...");
FAPI_DBG("Channel : %d, Operation : %d, No.of 8B Blocks of Data: %d",
i_ocb_chan, i_ocb_op, i_ocb_req_length);
@@ -253,7 +253,7 @@ fapi2::ReturnCode p9_pm_ocb_indir_access(
o_ocb_act_length);
}
- FAPI_IMP("Exit p9_pm_ocb_indir_access...");
+ FAPI_DBG("Exit p9_pm_ocb_indir_access...");
fapi_try_exit:
return fapi2::current_err;
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