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| author | Doug Gilbert <dgilbert@us.ibm.com> | 2016-08-19 18:02:39 -0500 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2016-09-09 08:47:14 -0400 |
| commit | a97202a9a4d328b8af4dd734d67df24cb6462333 (patch) | |
| tree | 29c2cc934d618c4af84635f480eafe6dd2a96654 | |
| parent | 429bb8ba92f196c3f20d1783d60ddadad6c6ec52 (diff) | |
| download | talos-sbe-a97202a9a4d328b8af4dd734d67df24cb6462333.tar.gz talos-sbe-a97202a9a4d328b8af4dd734d67df24cb6462333.zip | |
Set default MSR for performance
Change-Id: Ic53d48ed5254c751374bb6fd29ed9a5d9df109b6
RTC: 159553
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28572
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: YUE DU <daviddu@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28573
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
| -rw-r--r-- | src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42.h | 26 | ||||
| -rw-r--r-- | src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_msr.h | 2 |
2 files changed, 22 insertions, 6 deletions
diff --git a/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42.h b/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42.h index 6857ce10..66a05467 100644 --- a/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42.h +++ b/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42.h @@ -1,7 +1,7 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: import/chips/p9/procedures/ppe/pk/ppe42/ppe42.h $ */ +/* $Source: src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42.h $ */ /* */ /* OpenPOWER sbe Project */ /* */ @@ -287,17 +287,27 @@ popcount64(uint64_t x) // Application-overrideable definitions -/// The default thread machine context has MSR[CE], MSR[EE] and MSR[ME] set, +/// The default thread machine context has +// MSR[CE], MSR[EE] MSR[ME] MSR[IS0] MSR[IS1] MSR[IS2] set. +// MSR[IPE] is set if USE_PPE_IMPRECISE_MODE is defined. /// and all other MSR bits cleared. /// /// The default definition allows external and machine check exceptions. This /// definition can be overriden by the application. #ifndef PK_THREAD_MACHINE_CONTEXT_DEFAULT + +#if defined(USE_PPE_IMPRECISE_MODE) + #define PK_THREAD_MACHINE_CONTEXT_DEFAULT \ - (MSR_UIE | MSR_EE | MSR_ME) + (MSR_UIE | MSR_EE | MSR_ME | MSR_IS0 | MSR_IS1 | MSR_IS2 | MSR_IPE) +#else -#endif +#define PK_THREAD_MACHINE_CONTEXT_DEFAULT \ + (MSR_UIE | MSR_EE | MSR_ME | MSR_IS0 | MSR_IS1 | MSR_IS2) + +#endif /*USE_PPE_IMPRECISE_MODE*/ +#endif /*PK_THREAD_MACHINE_CONTEXT_DEFAULT*/ #ifndef __ASSEMBLER__ @@ -440,10 +450,14 @@ uint32_t __pk_panic_dbcr = DBCR_RST_HALT; /// PK_THREAD_MACHINE_CONTEXT_DEFAULT. This definition can be overriden by /// the application. /// -/// The default is to enable machine checks only. + #ifndef PPE42_MSR_INITIAL -#define PPE42_MSR_INITIAL MSR_ME +#if defined(USE_PPE_IMPRECISE_MODE) +#define PPE42_MSR_INITIAL (MSR_ME | MSR_IS0 | MSR_IS1 | MSR_IS2 | MSR_IPE) +#else +#define PPE42_MSR_INITIAL (MSR_ME | MSR_IS0 | MSR_IS1 | MSR_IS2) +#endif #endif /// The \a argc argument passed to \c main(). This definition can be overriden diff --git a/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_msr.h b/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_msr.h index a82b90b7..62ee04fd 100644 --- a/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_msr.h +++ b/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_msr.h @@ -49,6 +49,8 @@ #define MSR_UIE 0x00010000 /* Unmaskable Interrupt Enable */ #define MSR_EE 0x00008000 /* External Interrupt Enable */ #define MSR_ME 0x00001000 /* Machine Check Exception Enable */ +#define MSR_IS2 0x00000800 /* Instance-Specific field 2 */ +#define MSR_IS3 0x00000400 /* Instance-Specific field 3 */ #define MSR_IPE 0x00000100 /* Imprecise Mode Enable */ #define MSR_SIBRCA 0x000000ff /* SIB Return Code Accumulator */ |
