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| author | Zane Shelley <zshelle@us.ibm.com> | 2018-07-26 16:37:18 -0500 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2018-09-17 20:52:29 -0500 |
| commit | a29db3da08196fe07c0e85ab7bf5801fa9bdbf66 (patch) | |
| tree | aaf53dd7cb936f8e8bfd0ac9a7cc804ef5013cc2 | |
| parent | 43e1ba4a26432d3c91619c7917a90d2cbd285737 (diff) | |
| download | talos-sbe-a29db3da08196fe07c0e85ab7bf5801fa9bdbf66.tar.gz talos-sbe-a29db3da08196fe07c0e85ab7bf5801fa9bdbf66.zip | |
RAS_XML: updates to sync the XML with actual values from hardware
Change-Id: I590d6790cd391ff4be984001acd41c6a1ba48a06
CQ: SW445620
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63398
Reviewed-by: Caleb N. Palmer <cnpalmer@us.ibm.com>
Reviewed-by: Benjamin J. Weisenbeck <bweisenb@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63841
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C | 2 | ||||
| -rw-r--r-- | src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml | 18 |
2 files changed, 19 insertions, 1 deletions
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C index 431ba12a..1af6ded8 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C @@ -89,7 +89,7 @@ const uint64_t PBA_FIR_MASK = 0x3082448062FC0000ULL; // FBC const uint64_t FBC_PPE_FIR_ACTION0 = 0x0000000000000000ULL; const uint64_t FBC_PPE_FIR_ACTION1 = 0xF1C0000000000000ULL; -const uint64_t FBC_PPE_FIR_MASK = 0x0E1C000000000000ULL; +const uint64_t FBC_PPE_FIR_MASK = 0x0E3C000000000000ULL; // XBUS const uint64_t XB_PPE_FIR_ACTION0 = 0x0000000000000000ULL; const uint64_t XB_PPE_FIR_ACTION1 = 0xF1C0000000000000ULL; diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml index b13dafe6..06b16313 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml @@ -7791,6 +7791,24 @@ </attribute> <!-- ******************************************************************** --> <attribute> + <id>ATTR_CHIP_EC_FEATURE_CORE_RECOVERY_WA</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Unmask L2 FIR bit 39 to serve as PRD signalling mechanism + for core recovery + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_NIMBUS</name> + <ec> + <value>0x20</value> + <test>LESS_THAN</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <!-- ******************************************************************** --> + <attribute> <id>ATTR_CHIP_EC_FEATURE_SW432374</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description> |
