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| author | Joachim Fenkes <fenkes@de.ibm.com> | 2017-04-28 11:20:48 +0200 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2017-05-04 02:19:52 -0400 |
| commit | 8b4b61be507459e2938073b2361313d476736ddb (patch) | |
| tree | b4006ab2c37dacb41b5f0b756ac4eed415cc6200 | |
| parent | cc7e76c7c16cf1aac21128af07daa7f400aabdd6 (diff) | |
| download | talos-sbe-8b4b61be507459e2938073b2361313d476736ddb.tar.gz talos-sbe-8b4b61be507459e2938073b2361313d476736ddb.zip | |
p9_sbe_chiplet_reset: Revert NX_1 hang pulse back to 34s
The hang pulse setting of 68s is not supported by the PCB slave,
and NX can deal with a 34s hang pulse too, so revert back to 34s.
We could change the chiplet's base divider and adapt all other hang
pulse settings, but that would be a huge code ripup as it breaks
uniformity among chiplets.
Change-Id: I17ae92e58d713d54256083f43eabd9ce4be7167f
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39795
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39797
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C | 5 | ||||
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H | 1 |
2 files changed, 2 insertions, 4 deletions
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C index 27ac4020..f7ec5cf2 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C @@ -663,8 +663,8 @@ static fapi2::ReturnCode p9_sbe_chiplet_reset_all_cplt_hang_cnt_setup( l_data64.setBit<PERV_1_HANG_PULSE_1_REG_SUPPRESS>(); //HANG_PULSE_1_REG.SUPPRESS_HANG_1 = 1 FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_1_REG, l_data64)); //Setting HANG_PULSE_2_REG register value (Setting all fields) - //HANG_PULSE_2_REG.HANG_PULSE_REG_2 = p9SbeChipletReset::HANG_PULSE_0X23 - l_data64.insertFromRight<PERV_1_HANG_PULSE_2_REG_2, PERV_1_HANG_PULSE_2_REG_2_LEN>(p9SbeChipletReset::HANG_PULSE_0X23); + //HANG_PULSE_2_REG.HANG_PULSE_REG_2 = p9SbeChipletReset::HANG_PULSE_0X22 + l_data64.insertFromRight<PERV_1_HANG_PULSE_2_REG_2, PERV_1_HANG_PULSE_2_REG_2_LEN>(p9SbeChipletReset::HANG_PULSE_0X22); l_data64.setBit<PERV_1_HANG_PULSE_2_REG_SUPPRESS>(); //HANG_PULSE_2_REG.SUPPRESS_HANG_2 = 1 FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_2_REG, l_data64)); //Setting HANG_PULSE_3_REG register value (Setting all fields) @@ -1512,4 +1512,3 @@ static fapi2::ReturnCode p9_sbe_chiplet_reset_sectorbuffer_pulsemode_attr_setup( fapi_try_exit: return fapi2::current_err; } - diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H index d34e3780..f833f52b 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H @@ -69,7 +69,6 @@ enum P9_SBE_CHIPLET_RESET_Public_Constants HANG_PULSE_0X17 = 0x17, HANG_PULSE_0X18 = 0x18, HANG_PULSE_0X22 = 0x22, - HANG_PULSE_0X23 = 0x23, HANG_PULSE_0X13 = 0x13, HANG_PULSE_0X03 = 0x03, OPCG_ALIGN_SETTING = 0x5000000000003020ull, |
