Ensure SGPE is disabled and ensure writes are enabled during pm_suspend

Previously if the PGPE was halted the pm_suspend HWP would not do anything.
This caused and issue if an MPIPL was triggered in a window where the SGPE
was running but the PGPE was not. This commit adds a check to see if the
SGPE isnt halted, and the PGPE is, if that is true then the SGPE gets
halted via the XIXCR. In addition to this change we have were seeing
issues where if an MPIPL was triggered in the window where SGPE isnt halted
and the PGPE is, then the PCB_WRITE_DISABLE bit was never getting cleared
which caused problems when we tried to power down the quads.

Change-Id: If2c67ce1153a949527b8e9f2cfcba1e0fe04c398
CQ: SW398122
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45444
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45448
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>

2 files changed, 28 insertions, 13 deletions

diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.C
index f7997e9e..583a34fc 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.C
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.C
@@ -184,15 +184,6 @@ fapi2::ReturnCode p9_sbe_select_ex(
     auto l_eq_functional_vector = i_target.getChildren<fapi2::TARGET_TYPE_EQ>
                                   (fapi2::TARGET_STATE_FUNCTIONAL );
 
-    // Prior to writing to PM registers, ensure that the PPM write disable
-    // bit on the Core Power Management Mode Register is cleared for all cores
-    for (auto& core : l_core_functional_vector)
-    {
-        FAPI_DBG("Clearing WRITE_DISABLE bit in core %d", core.getChipletNumber());
-        l_data64.flush<0>().setBit<C_CPPM_CPMMR_PPM_WRITE_DISABLE>();
-        FAPI_TRY(fapi2::putScom(core, C_CPPM_CPMMR_CLEAR , l_data64));
-    }
-
     // Read the "FORCE_ALL" attribute
     fapi2::ATTR_SYS_FORCE_ALL_CORES_Type l_attr_force_all;
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYS_FORCE_ALL_CORES,
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_suspend_powman.C b/src/import/chips/p9/procedures/hwp/pm/p9_suspend_powman.C
index e2e1857f..f9c54d7e 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_suspend_powman.C
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_suspend_powman.C
@@ -75,15 +75,18 @@ extern "C" {
         fapi2::buffer<uint64_t> l_occflg_data(0);
         fapi2::buffer<uint64_t> l_occs2_data(0);
         fapi2::buffer<uint64_t> l_ocr_reg_data(0);
-        fapi2::buffer<uint64_t> l_pgpe_xsr(0);
+        fapi2::buffer<uint64_t> l_xsr(0);
+        fapi2::buffer<uint64_t> l_data64 = 0;
+        auto l_core_vector = i_target.getChildren<fapi2::TARGET_TYPE_CORE>();
+        static const uint64_t  PPE_XIXCR_XCR_HALT      = 0x1000000000000000;
 
         bool l_pgpe_in_safe_mode = false;
         bool l_pgpe_suspended = false;
 
-        FAPI_TRY(fapi2::getScom(i_target, PU_GPE2_GPEXIXSR_SCOM, l_pgpe_xsr),
+        FAPI_TRY(fapi2::getScom(i_target, PU_GPE2_GPEXIXSR_SCOM, l_xsr),
                  "Error checking PGPE XSR");
 
-        if(!(l_pgpe_xsr >> 63))
+        if(!(l_xsr >> 63))
         {
 
             // SBE waits for PGPE to set OCC Scratch2[PGPE_SAFE_MODE_ACTIVE]
@@ -162,7 +165,28 @@ extern "C" {
         }
         else
         {
-            FAPI_INF("WARNING! PGPE Already Halted, skipping procedure");
+            FAPI_TRY(fapi2::getScom(i_target, PU_GPE3_GPEXIXSR_SCOM, l_xsr),
+                     "Error reading SGPE XSR");
+
+            //Make sure that the SGPE is not halted before requesting halt
+            if(!(l_xsr >> 63))
+            {
+                FAPI_INF("WARNING! PGPE Already Halted, halting SGPE via XIXSR");
+                FAPI_TRY(fapi2::putScom(i_target, PU_GPE3_GPEXIXCR_SCOM, PPE_XIXCR_XCR_HALT));
+            }
+            else
+            {
+                FAPI_INF("WARNING! SGPE and PGPE Already Halted, skipping procedure");
+            }
+        }
+
+        // Ensure that the PPM write disable bit on the Core Power Management Mode Register
+        // is cleared for all cores
+        for (auto& core : l_core_vector)
+        {
+            FAPI_INF("Clearing WRITE_DISABLE bit in core %d", core.getChipletNumber());
+            l_data64.flush<0>().setBit<C_CPPM_CPMMR_PPM_WRITE_DISABLE>();
+            FAPI_TRY(fapi2::putScom(core, C_CPPM_CPMMR_CLEAR , l_data64));
         }
 
     fapi_try_exit: