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authorAnusha Reddy Rangareddygari <anusrang@in.ibm.com>2016-01-21 13:57:15 +0100
committerSachin Gupta <sgupta2m@in.ibm.com>2017-10-23 08:31:33 -0400
commit701c3b882d41c4193e20dc620a4c8cd4fa66b463 (patch)
treea9c11c23e7fbbefcdb60b2af18143247b862634c
parent9d874a063fae75adccb46bf3d2ed138c40aca887 (diff)
downloadtalos-sbe-701c3b882d41c4193e20dc620a4c8cd4fa66b463.tar.gz
talos-sbe-701c3b882d41c4193e20dc620a4c8cd4fa66b463.zip
Level 2 HWP for p9_setup_clock_term
Also included wrap files and makefiles Change-Id: I228028a5af319ebda4343e5cf39b3f2618162470 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/23474 Tested-by: Jenkins Server Dev-Ready: Brent Wieman <bwieman@us.ibm.com> Reviewed-by: Manish K. Chowdhary <manichow@in.ibm.com> Reviewed-by: Sunil Kumar <skumar8j@in.ibm.com> Reviewed-by: Parvathi Rachakonda Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48500 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
-rw-r--r--src/import/chips/p9/procedures/hwp/perv/p9_setup_clock_term.H49
1 files changed, 36 insertions, 13 deletions
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_setup_clock_term.H b/src/import/chips/p9/procedures/hwp/perv/p9_setup_clock_term.H
index 5b6b1baa..77913892 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_setup_clock_term.H
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_setup_clock_term.H
@@ -25,16 +25,14 @@
//------------------------------------------------------------------------------
/// @file p9_setup_clock_term.H
///
-/// @brief proc setup clock term
-// *!
-// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com
-// *! BACKUP NAME : Email:
+/// @brief Setup the clock termination correctly for system/chip type
//------------------------------------------------------------------------------
-// *HWP HWP Owner : Abhishek Agarwal <abagarw8@in.ibm.com>
-// *HWP FW Owner : Brian Silver <bsilver@us.ibm.com>
-// *HWP Team : Perv
-// *HWP Level : 1
-// *HWP Consumed by : SBE
+// *HWP HW Owner : Anusha Reddy Rangareddygari <anusrang@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner : Brian Silver <bsilver@us.ibm.com>
+// *HWP Team : Perv
+// *HWP Level : 2
+// *HWP Consumed by : FSP:HB
//------------------------------------------------------------------------------
@@ -45,18 +43,43 @@
#include <fapi2.H>
+namespace p9SetupClockTerm
+{
+enum P9_SETUP_CLOCK_TERM_Public_Constants
+{
+ OSCSWITCH_RC3 = 0x0080C000,
+ OSCSWITCH_RC4 = 0x0
+};
+}
+
+typedef enum { BOTH_SRC0, BOTH_SRC1, SRC0, SRC1, SRC_NONE } pci_clk_req_enum;
+
+// pci_clk_req_enum enumarated data type with allowed PCI refclock configurations
+// BOTH_SRC0: redundant PCI clock available, SRC0 configured as primary source
+// BOTH_SRC1: redundant PCI clock available, SRC1 configured as primary source
+// SRC0: redundant PCI clock but forced to use SRC0 only as other clock may be garded/deconfigured
+// SRC1: redundant PCI clock but forced to use SRC1 only as other clock may be garded/deconfigured
+// SRC_NONE: non-redundant PCI clock setup
+
+
+
typedef fapi2::ReturnCode (*p9_setup_clock_term_FP_t)(const
- fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&);
+ fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&, const pci_clk_req_enum);
-/// @brief Setup the clock termination correctly for system/chip type
-/// Since this is the first procedure run against the chips it also clears the GP write protect
+/// @brief Setup the clock termination correctly, since this is the first procedure run against the chips it also clears the GP write protect
///
/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target
+// pci_clk_req_enum enumarated data type with allowed PCI refclock configurations
+// BOTH_SRC0: redundant PCI clock available, SRC0 configured as primary source
+// BOTH_SRC1: redundant PCI clock available, SRC1 configured as primary source
+// SRC0: redundant PCI clock but forced to use SRC0 only as other clock may be garded/deconfigured
+// SRC1: redundant PCI clock but forced to use SRC1 only as other clock may be garded/deconfigured
+// SRC_NONE: non-redundant PCI clock setup
/// @return FAPI2_RC_SUCCESS if success, else error code.
extern "C"
{
fapi2::ReturnCode p9_setup_clock_term(const
- fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip);
+ fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip, const pci_clk_req_enum i_pci_clk_req);
}
#endif
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