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| author | Alex Taft <amtaft@us.ibm.com> | 2017-06-01 10:44:18 -0500 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2017-06-13 00:12:51 -0400 |
| commit | 5cf1886ced7a65542186524d308fede55cc322b1 (patch) | |
| tree | 0245ed19446f76ee679fe52aeef3c039b542cb81 | |
| parent | 6e46f6ae14fe694c4fa750777ba9d78c8de16c92 (diff) | |
| download | talos-sbe-5cf1886ced7a65542186524d308fede55cc322b1.tar.gz talos-sbe-5cf1886ced7a65542186524d308fede55cc322b1.zip | |
L3 initfile updates
The following should apply to all chips/systems.
1) Set edram refresh divider to optimal value based on
pb frequency
2) performance fix for castout pacing. Base value was too
high.
Change-Id: I7f280f9826ba7483a31b64aca5caf36affaea843
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41248
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: ALEXANDER M. TAFT <amtaft@us.ibm.com>
Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41253
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/initfiles/p9_l3_scom.C | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_l3_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_l3_scom.C index 9177e051..4585c41d 100644 --- a/src/import/chips/p9/procedures/hwp/initfiles/p9_l3_scom.C +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_l3_scom.C @@ -29,6 +29,7 @@ using namespace fapi2; +constexpr uint64_t literal_3 = 3; constexpr uint64_t literal_1 = 1; constexpr uint64_t literal_8 = 8; constexpr uint64_t literal_0b0 = 0b0; @@ -44,6 +45,8 @@ fapi2::ReturnCode p9_l3_scom(const fapi2::Target<fapi2::TARGET_TYPE_EX>& TGT0, fapi2::ATTR_NAME_Type l_chip_id; FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_NAME, TGT2, l_chip_id)); FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_EC, TGT2, l_chip_ec)); + fapi2::ATTR_NEST_PLL_BUCKET_Type l_TGT1_ATTR_NEST_PLL_BUCKET; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_NEST_PLL_BUCKET, TGT1, l_TGT1_ATTR_NEST_PLL_BUCKET)); uint64_t l_def_L3_EPS_DIVIDE = literal_1; fapi2::ATTR_PROC_EPS_READ_CYCLES_T0_Type l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T0; FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_READ_CYCLES_T0, TGT1, l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T0)); @@ -61,6 +64,17 @@ fapi2::ReturnCode p9_l3_scom(const fapi2::Target<fapi2::TARGET_TYPE_EX>& TGT0, FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_PUMP_MODE, TGT1, l_TGT1_ATTR_PROC_FABRIC_PUMP_MODE)); fapi2::buffer<uint64_t> l_scom_buffer; { + FAPI_TRY(fapi2::getScom( TGT0, 0x1001180full, l_scom_buffer )); + + if ((l_TGT1_ATTR_NEST_PLL_BUCKET >= literal_3)) + { + constexpr auto l_EXP_L3_L3_CARB_L3CACTL_L3_REF_TIMER_DIVIDE_MINOR_DIV_BY_12 = 0x2; + l_scom_buffer.insert<8, 4, 60, uint64_t>(l_EXP_L3_L3_CARB_L3CACTL_L3_REF_TIMER_DIVIDE_MINOR_DIV_BY_12 ); + } + + FAPI_TRY(fapi2::putScom(TGT0, 0x1001180full, l_scom_buffer)); + } + { FAPI_TRY(fapi2::getScom( TGT0, 0x10011829ull, l_scom_buffer )); l_scom_buffer.insert<0, 12, 52, uint64_t>((((l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T0 / literal_8) / l_def_L3_EPS_DIVIDE) + |
