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authorAnusha Reddy Rangareddygari <anusrang@in.ibm.com>2016-07-19 10:43:17 +0200
committerSachin Gupta <sgupta2m@in.ibm.com>2016-07-21 03:11:54 -0400
commit5337ac94b9c22775a03a6584c0d2be321daf90bc (patch)
tree6a986d3182a289e8bc7cb4613658bb9fc3be5184
parenta058c58733a6f15387cb95fd0ed3823ede85b4ad (diff)
downloadtalos-sbe-5337ac94b9c22775a03a6584c0d2be321daf90bc.tar.gz
talos-sbe-5337ac94b9c22775a03a6584c0d2be321daf90bc.zip
Level 2 HWP for p9_hcd_cache_chiplet_l3_dcc_setup
Change-Id: Ia9877b2fc0e4eaf2a72f04434f24ec82ddd0727d Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27175 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27178 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
-rw-r--r--import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_l3_dcc_setup.C36
-rw-r--r--import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_l3_dcc_setup.H2
-rw-r--r--import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml4
-rw-r--r--import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml13
4 files changed, 50 insertions, 5 deletions
diff --git a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_l3_dcc_setup.C b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_l3_dcc_setup.C
index 8de85c52..64a23aa2 100644
--- a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_l3_dcc_setup.C
+++ b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_l3_dcc_setup.C
@@ -25,7 +25,7 @@
// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
// *HWP FW Owner : Sunil Kumar <skumar8j@in.ibm.com>
// *HWP Team : Perv
-// *HWP Level : 1
+// *HWP Level : 2
// *HWP Consumed by : SBE
//------------------------------------------------------------------------------
@@ -33,15 +33,43 @@
//## auto_generated
#include "p9_hcd_cache_chiplet_l3_dcc_setup.H"
+#include <p9_quad_scom_addresses.H>
+#include <p9_quad_scom_addresses_fld.H>
fapi2::ReturnCode p9_hcd_cache_chiplet_l3_dcc_setup(const
fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target_chiplet)
{
- FAPI_INF("Entering ...");
+ const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM;
+ fapi2::buffer<uint64_t> l_data64;
+ uint8_t l_read_attr = 0;
+ FAPI_DBG("Entering ...");
- FAPI_INF("Exiting ...");
+ FAPI_TRY(fapi2::putRing(i_target_chiplet, eq_ana_bndy_l3dcc_bucket_26, fapi2::RING_MODE_SET_PULSE_NSL));
- return fapi2::FAPI2_RC_SUCCESS;
+ FAPI_DBG("Drop L3 DCC bypass");
+ //Setting NET_CTRL1 register value
+ l_data64.flush<1>();
+ //NET_CTRL1.CLK_DCC_BYPASS_EN = 0
+ l_data64.clearBit<C_NET_CTRL1_CLK_DCC_BYPASS_EN>();
+ FAPI_TRY(fapi2::putScom(i_target_chiplet, EQ_NET_CTRL1_WAND, l_data64));
+
+ FAPI_DBG("Check if VDMs are to be enabled. If so, power them on");
+ FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_VDM_ENABLE, FAPI_SYSTEM,
+ l_read_attr));
+
+ if( l_read_attr )
+ {
+
+ l_data64.flush<0>();
+ l_data64.setBit<0>();
+ FAPI_TRY(fapi2::putScom(i_target_chiplet, EQ_PPM_VDMCR_OR, l_data64));
+
+ }
+
+ FAPI_DBG("Exiting ...");
+
+fapi_try_exit:
+ return fapi2::current_err;
}
diff --git a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_l3_dcc_setup.H b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_l3_dcc_setup.H
index 506923c6..fe361d0a 100644
--- a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_l3_dcc_setup.H
+++ b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_l3_dcc_setup.H
@@ -25,7 +25,7 @@
// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
// *HWP FW Owner : Sunil Kumar <skumar8j@in.ibm.com>
// *HWP Team : Perv
-// *HWP Level : 1
+// *HWP Level : 2
// *HWP Consumed by : SBE
//------------------------------------------------------------------------------
diff --git a/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml b/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml
index 5b1b33ee..ce579484 100644
--- a/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml
+++ b/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml
@@ -484,6 +484,10 @@
<name>ATTR_IO_FILTER_BYPASS</name>
<value>0x0</value>
</entry>
+ <entry>
+ <name>ATTR_VDM_ENABLE</name>
+ <value>0x0</value>
+ </entry>
<!-- See chip_attributes.xml for a description of ATTR_EC -->
<entry>
<name>ATTR_EC</name>
diff --git a/import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml b/import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml
index 835866be..1e6f60f7 100644
--- a/import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml
+++ b/import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml
@@ -963,4 +963,17 @@
<initToZero/>
<platInit/>
</attribute>
+ <!-- ********************************************************************* -->
+ <attribute>
+ <id>ATTR_VDM_ENABLE</id>
+ <targetType>TARGET_TYPE_SYSTEM</targetType>
+ <description>Controls the enablement of Voltage Droop Monitors in the system
+ Producer:Machine Readable Workbook
+ Consumers:p9_pstate_parameter_block to set flag for CME QuadManager Hcode reaction
+ p9_hcd_cache procedures to power on VDMs before CME booting
+ </description>
+ <valueType>uint8</valueType>
+ <platInit/>
+</attribute>
+
</attributes>
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