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author | Santosh Puranik <santosh.puranik@in.ibm.com> | 2017-01-17 10:39:05 -0600 |
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committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2017-10-27 21:47:34 -0400 |
commit | 2e4607a018b70e3019155e642d7f07ab2c9d4905 (patch) | |
tree | a226825b70c6b77755e823cb7e65ae0a0546b6ea | |
parent | 3a7ffbc58d55b4c5b4afff69123e083d6b808da8 (diff) | |
download | talos-sbe-2e4607a018b70e3019155e642d7f07ab2c9d4905.tar.gz talos-sbe-2e4607a018b70e3019155e642d7f07ab2c9d4905.zip |
Make plat init attributes non-writable
Change-Id: I382948a4083293e4ecc42a9759559a060444f5f0
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34997
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35043
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
-rw-r--r-- | src/hwpf/plat_target_utils.H | 4 | ||||
-rw-r--r-- | src/hwpf/target.C | 279 | ||||
-rw-r--r-- | src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C | 243 | ||||
-rw-r--r-- | src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml | 23 | ||||
-rw-r--r-- | src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_load_bootloader_attributes.xml | 1 | ||||
-rwxr-xr-x | src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml | 52 | ||||
-rw-r--r-- | src/sbefw/sbecmdgeneric.C | 2 | ||||
-rw-r--r-- | src/sbefw/sbecmdiplcontrol.C | 10 | ||||
-rw-r--r-- | src/sbefw/sbemain.C | 10 | ||||
-rw-r--r-- | src/sbefw/sberegaccess.C | 2 |
10 files changed, 306 insertions, 320 deletions
diff --git a/src/hwpf/plat_target_utils.H b/src/hwpf/plat_target_utils.H index 0a2d525d..bb46ccec 100644 --- a/src/hwpf/plat_target_utils.H +++ b/src/hwpf/plat_target_utils.H @@ -49,6 +49,10 @@ namespace fapi2 /// attributes ReturnCode plat_TargetsInit(); + /// @brief Initializes all platInit attributes (the values for which come + // from the scratch registers) + ReturnCode plat_AttrInit(); + /// @brief Function to apply any gard records set (via // ATTR_EQ_GARD/ATTR_EC_GARD) to mark corresponding targets non functional ReturnCode plat_ApplyGards(); diff --git a/src/hwpf/target.C b/src/hwpf/target.C index 42806095..dfcd7bd8 100644 --- a/src/hwpf/target.C +++ b/src/hwpf/target.C @@ -47,7 +47,7 @@ fapi2attr::EXAttributes_t* G_ex_attributes_ptr; namespace fapi2 { - static ReturnCode plat_AttrInit() + ReturnCode plat_AttrInit() { union { @@ -69,8 +69,284 @@ namespace fapi2 uint8_t l_chipName = fapi2::ENUM_ATTR_NAME_NONE; uint8_t l_ec = 0; uint8_t fusedMode = 0; + fapi2::buffer<uint64_t> l_tempReg = 0; + fapi2::buffer<uint64_t> l_scratch8Reg = 0; + fapi2::buffer<uint8_t> l_read1 = 0; + fapi2::buffer<uint8_t> l_read2 = 0; + fapi2::buffer<uint8_t> l_read3 = 0; + fapi2::buffer<uint16_t> l_read4 = 0; + fapi2::buffer<uint32_t> l_read5 = 0; + fapi2::buffer<uint64_t> l_deviceIdReg = 0; + bool l_isSlave = false; fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_chipTarget = plat_getChipTarget(); + const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; + + //Getting SCRATCH_REGISTER_8 register value + FAPI_TRY(fapi2::getScom(l_chipTarget, PERV_SCRATCH_REGISTER_8_SCOM, + l_scratch8Reg)); + + //Getting CBS_CS register value + FAPI_TRY(fapi2::getScom(l_chipTarget, PERV_CBS_CS_SCOM, + l_tempReg)); + + l_read1.writeBit<7>(l_tempReg.getBit<4>()); + + FAPI_DBG("Setting ATTR_SECURITY_ENABLE with the SAB state"); + FAPI_TRY(PLAT_ATTR_INIT(fapi2::ATTR_SECURITY_ENABLE, FAPI_SYSTEM, l_read1)); + + if ( l_scratch8Reg.getBit<0>() ) + { + FAPI_DBG("Reading Scratch_reg1"); + //Getting SCRATCH_REGISTER_1 register value + FAPI_TRY(fapi2::getScom(l_chipTarget, PERV_SCRATCH_REGISTER_1_SCOM, + l_tempReg)); + + l_tempReg.extract<0, 6>(l_read1); + l_tempReg.extract<8, 24>(l_read5); + + FAPI_DBG("Setting up ATTR_EQ_GARD, ATTR_EC_GARD"); + FAPI_TRY(PLAT_ATTR_INIT(fapi2::ATTR_EQ_GARD, l_chipTarget, l_read1)); + FAPI_TRY(PLAT_ATTR_INIT(fapi2::ATTR_EC_GARD, l_chipTarget, l_read5)); + + l_read1 = 0; + l_read5 = 0; + } + if ( l_scratch8Reg.getBit<1>() ) + { + uint8_t l_ob0PllBucket = 0; + uint8_t l_ob1PllBucket = 0; + uint8_t l_ob2PllBucket = 0; + uint8_t l_ob3PllBucket = 0; + uint8_t l_ndlMeshctrlSetup = 0x0; + + FAPI_DBG("Reading Scratch_reg2"); + //Getting SCRATCH_REGISTER_2 register value + FAPI_TRY(fapi2::getScom(l_chipTarget, PERV_SCRATCH_REGISTER_2_SCOM, + l_tempReg)); + + l_tempReg.extractToRight<0, 16>(l_read4); + l_tempReg.extractToRight<24, 2>(l_ob0PllBucket); + l_tempReg.extractToRight<26, 2>(l_ob1PllBucket); + l_tempReg.extractToRight<28, 2>(l_ob2PllBucket); + l_tempReg.extractToRight<30, 2>(l_ob3PllBucket); + l_tempReg.extractToRight<21, 3>(l_read1); + + // Workaround to handle backward compatibilty + // Old drivers will keep MBX OBUS PLL bucket value as zero. So + // change it to 1 to make old drivers compatible with new SBE + // image + if( 0 == l_ob0PllBucket ) + { + l_ob0PllBucket = 1; + } + + if( 0 == l_ob1PllBucket ) + { + l_ob1PllBucket = 1; + } + + if( 0 == l_ob2PllBucket ) + { + l_ob2PllBucket = 1; + } + + if( 0 == l_ob3PllBucket ) + { + l_ob3PllBucket = 1; + } + + FAPI_DBG("Setting up ATTR_I2C_BUS_DIV_REF"); + FAPI_TRY(PLAT_ATTR_INIT(fapi2::ATTR_I2C_BUS_DIV_REF, l_chipTarget, l_read4)); + + l_tempReg.extractToRight<16, 4>(l_ndlMeshctrlSetup); + l_ndlMeshctrlSetup = (~l_ndlMeshctrlSetup) & 0x0F; + FAPI_DBG("Setting up ATTR_NDL_MESHCTRL_SETUP"); + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_NDL_MESHCTRL_SETUP, l_chipTarget, l_ndlMeshctrlSetup)); + + FAPI_DBG("Setting up ATTR_MC_PLL_BUCKET"); + FAPI_TRY(PLAT_ATTR_INIT(fapi2::ATTR_MC_PLL_BUCKET, FAPI_SYSTEM, l_read1)); + + FAPI_DBG("Setting up ATTR_OBX_PLL_BUCKET"); + FAPI_TRY(PLAT_ATTR_INIT(fapi2::ATTR_OB0_PLL_BUCKET, l_chipTarget, l_ob0PllBucket)); + FAPI_TRY(PLAT_ATTR_INIT(fapi2::ATTR_OB1_PLL_BUCKET, l_chipTarget, l_ob1PllBucket)); + FAPI_TRY(PLAT_ATTR_INIT(fapi2::ATTR_OB2_PLL_BUCKET, l_chipTarget, l_ob2PllBucket)); + FAPI_TRY(PLAT_ATTR_INIT(fapi2::ATTR_OB3_PLL_BUCKET, l_chipTarget, l_ob3PllBucket)); + } + + if ( l_scratch8Reg.getBit<2>() ) + { + uint8_t l_isMpIpl = 0; + uint8_t l_isSpMode = 0; + FAPI_DBG("Reading Scratch_reg3"); + //Getting SCRATCH_REGISTER_3 register value + FAPI_TRY(fapi2::getScom(l_chipTarget, PERV_SCRATCH_REGISTER_3_SCOM, + l_tempReg)); + + l_tempReg.extractToRight<2, 1>(l_isMpIpl); + + FAPI_DBG("Setting up ATTR_IS_MPIPL"); + FAPI_TRY(PLAT_ATTR_INIT(fapi2::ATTR_IS_MPIPL, FAPI_SYSTEM, l_isMpIpl)); + + l_tempReg.extractToRight<3, 1>(l_isSpMode); + + FAPI_DBG("Setting up ATTR_IS_SP_MODE"); + FAPI_TRY(PLAT_ATTR_INIT(fapi2::ATTR_IS_SP_MODE, l_chipTarget, l_isSpMode)); + } + + if ( l_scratch8Reg.getBit<3>() ) + { + uint8_t l_cpFilterBypass = 0; + uint8_t l_ssFilterBypass = 0; + uint8_t l_ioFilterBypass = 0; + uint8_t l_dpllBypass = 0; + uint8_t l_nestMemXOPciBypass = 0; + uint8_t l_attrObusRatio = 0; + + FAPI_DBG("Reading Scratch_Reg4"); + //Getting SCRATCH_REGISTER_4 register value + FAPI_TRY(fapi2::getScom(l_chipTarget, PERV_SCRATCH_REGISTER_4_SCOM, + l_tempReg)); + + l_tempReg.extractToRight<0, 16>(l_read4); + l_tempReg.extractToRight<16, 1>(l_cpFilterBypass); + l_tempReg.extractToRight<17, 1>(l_ssFilterBypass); + l_tempReg.extractToRight<18, 1>(l_ioFilterBypass); + l_tempReg.extractToRight<19, 1>(l_dpllBypass); + l_tempReg.extractToRight<20, 1>(l_nestMemXOPciBypass); + l_tempReg.extractToRight<21, 1>(l_attrObusRatio); + l_tempReg.extractToRight<24, 8>(l_read1); + + FAPI_DBG("Setting up PLL bypass attributes"); + FAPI_TRY(PLAT_ATTR_INIT(fapi2::ATTR_CP_FILTER_BYPASS, l_chipTarget, l_cpFilterBypass)); + FAPI_TRY(PLAT_ATTR_INIT(fapi2::ATTR_SS_FILTER_BYPASS, l_chipTarget, l_ssFilterBypass)); + FAPI_TRY(PLAT_ATTR_INIT(fapi2::ATTR_IO_FILTER_BYPASS, l_chipTarget, l_ioFilterBypass)); + FAPI_TRY(PLAT_ATTR_INIT(fapi2::ATTR_DPLL_BYPASS, l_chipTarget, l_dpllBypass)); + FAPI_TRY(PLAT_ATTR_INIT(fapi2::ATTR_NEST_MEM_X_O_PCI_BYPASS, l_chipTarget, l_nestMemXOPciBypass)); + FAPI_DBG("Setting up ATTR_BOOT_FREQ_MULT, ATTR_NEST_PLL_BUCKET"); + FAPI_TRY(PLAT_ATTR_INIT(fapi2::ATTR_BOOT_FREQ_MULT, l_chipTarget, l_read4)); + FAPI_TRY(PLAT_ATTR_INIT(fapi2::ATTR_NEST_PLL_BUCKET, FAPI_SYSTEM, l_read1)); + + FAPI_DBG("Setting up ATTR_OBUS_RATIO_VALUE"); + FAPI_TRY(PLAT_ATTR_INIT(fapi2::ATTR_OBUS_RATIO_VALUE, l_chipTarget, l_attrObusRatio)); + + l_read1 = 0; + l_read4 = 0; + } + + if ( l_scratch8Reg.getBit<4>() ) + { + uint8_t l_forceAllCores = 0; + uint8_t l_riskLevel = 0; + uint8_t l_disableHbblVectors = 0; + uint32_t l_pllMux = 0; + uint8_t l_mcSyncMode = 0; + uint8_t l_slowPciRefClock = 0; + + FAPI_DBG("Reading Scratch_reg5"); + //Getting SCRATCH_REGISTER_5 register value + FAPI_TRY(fapi2::getScom(l_chipTarget, PERV_SCRATCH_REGISTER_5_SCOM, + l_tempReg)); + + l_tempReg.extract<1, 1, 7>(l_forceAllCores); + + if (l_tempReg.getBit<2>()) + { + l_riskLevel = fapi2::ENUM_ATTR_RISK_LEVEL_TRUE; + } + else + { + l_riskLevel = fapi2::ENUM_ATTR_RISK_LEVEL_FALSE; + } + + if (l_tempReg.getBit<3>()) + { + l_disableHbblVectors = fapi2::ENUM_ATTR_DISABLE_HBBL_VECTORS_TRUE; + } + else + { + l_disableHbblVectors = fapi2::ENUM_ATTR_DISABLE_HBBL_VECTORS_FALSE; + } + + l_tempReg.extract<12, 20, 0>(l_pllMux); + + l_tempReg.extract<4, 1, 7>(l_mcSyncMode); + + if (l_tempReg.getBit<5>()) + { + l_slowPciRefClock = fapi2::ENUM_ATTR_DD1_SLOW_PCI_REF_CLOCK_NORMAL; + } + else + { + l_slowPciRefClock = fapi2::ENUM_ATTR_DD1_SLOW_PCI_REF_CLOCK_SLOW; + } + + FAPI_DBG("Setting up RISK_LEVEL, SYS_FORCE_ALL_CORES"); + FAPI_TRY(PLAT_ATTR_INIT(fapi2::ATTR_SYS_FORCE_ALL_CORES, FAPI_SYSTEM, l_forceAllCores)); + FAPI_TRY(PLAT_ATTR_INIT(fapi2::ATTR_RISK_LEVEL, FAPI_SYSTEM, l_riskLevel)); + FAPI_TRY(PLAT_ATTR_INIT(fapi2::ATTR_DISABLE_HBBL_VECTORS, FAPI_SYSTEM, l_disableHbblVectors)); + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_MC_SYNC_MODE, l_chipTarget, l_mcSyncMode)); + FAPI_TRY(PLAT_ATTR_INIT(fapi2::ATTR_DD1_SLOW_PCI_REF_CLOCK, FAPI_SYSTEM, l_slowPciRefClock)); + FAPI_TRY(PLAT_ATTR_INIT(fapi2::ATTR_CLOCK_PLL_MUX, l_chipTarget, l_pllMux)); + } + + if ( l_scratch8Reg.getBit<5>() ) + { + uint8_t l_pumpMode = fapi2::ENUM_ATTR_PROC_FABRIC_PUMP_MODE_CHIP_IS_NODE; + + FAPI_DBG("Reading Scratch_reg6"); + //Getting SCRATCH_REGISTER_6 register value + FAPI_TRY(fapi2::getScom(l_chipTarget, PERV_SCRATCH_REGISTER_6_SCOM, + l_tempReg)); + + l_read1 = 0; + l_isSlave = l_tempReg.getBit<24>(); + + if ( !l_isSlave ) // 0b0 == master + { + FAPI_DBG("Reading DEVICE_ID_REG value"); + FAPI_TRY(fapi2::getScom(l_chipTarget, PERV_DEVICE_ID_REG, l_deviceIdReg)); + + if (!l_deviceIdReg.getBit<40>()) + { + l_read1.setBit<7>(); + } + } + + if (l_tempReg.getBit<23>()) + { + l_pumpMode = fapi2::ENUM_ATTR_PROC_FABRIC_PUMP_MODE_CHIP_IS_GROUP; + } + else + { + l_pumpMode = fapi2::ENUM_ATTR_PROC_FABRIC_PUMP_MODE_CHIP_IS_NODE; + } + + l_tempReg.extractToRight<26, 3>(l_read2); + l_tempReg.extractToRight<29, 3>(l_read3); + + FAPI_DBG("Setting up PUMP MODE"); + FAPI_TRY(PLAT_ATTR_INIT(fapi2::ATTR_PROC_FABRIC_PUMP_MODE, + fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), + l_pumpMode)); + + FAPI_DBG("Setting up MASTER_CHIP, FABRIC_GROUP_ID and CHIP_ID"); + FAPI_TRY(PLAT_ATTR_INIT(fapi2::ATTR_PROC_SBE_MASTER_CHIP, l_chipTarget, + l_read1)); + FAPI_TRY(PLAT_ATTR_INIT(fapi2::ATTR_PROC_FABRIC_GROUP_ID, l_chipTarget, + l_read2)); + FAPI_TRY(PLAT_ATTR_INIT(fapi2::ATTR_PROC_FABRIC_CHIP_ID, l_chipTarget, + l_read3)); + + l_tempReg.extractToRight<17, 3>(l_read2); + l_tempReg.extractToRight<20, 3>(l_read3); + + FAPI_TRY(PLAT_ATTR_INIT(fapi2::ATTR_PROC_EFF_FABRIC_GROUP_ID, l_chipTarget, + l_read2)); + FAPI_TRY(PLAT_ATTR_INIT(fapi2::ATTR_PROC_EFF_FABRIC_CHIP_ID, l_chipTarget, + l_read3)); + } + FAPI_TRY(getscom_abs(PERV_DEVICE_ID_REG, &l_deviceId.iv_deviceIdReg)); l_ec = (l_deviceId.iv_majorEC << 4) | (l_deviceId.iv_minorEC); @@ -784,5 +1060,4 @@ fapi_try_exit: fapi_try_exit: return fapi2::current_err; } - } // fapi2 diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C index 223b063c..697978f1 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C @@ -110,14 +110,11 @@ fapi2::ReturnCode p9_sbe_attr_setup(const fapi2::buffer<uint64_t> l_read_scratch8 = 0; fapi2::buffer<uint8_t> l_read_1 = 0; fapi2::buffer<uint8_t> l_read_2 = 0; - fapi2::buffer<uint8_t> l_read_3 = 0; fapi2::buffer<uint16_t> l_read_4 = 0; fapi2::buffer<uint32_t> l_read_5 = 0; fapi2::buffer<uint32_t> l_read_6 = 0; const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; fapi2::buffer<uint64_t> l_data64; - bool sbe_slave_chip = false; - fapi2::buffer<uint64_t> l_read_device_reg = 0; FAPI_INF("p9_sbe_attr_setup: Entering ..."); FAPI_DBG("Read Scratch8 for validity of Scratch register"); @@ -164,33 +161,10 @@ fapi2::ReturnCode p9_sbe_attr_setup(const l_secure_settings.secureAccessBit = l_read_reg.getBit<4>(); FAPI_DBG("Setting up ATTR_SECURITY_SETTINGS"); FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_SECURE_SETTINGS, FAPI_SYSTEM, l_secure_settings.data8)); - - l_read_1 = 0; - l_read_1.writeBit<7>(l_read_reg.getBit<4>()); - - FAPI_DBG("Setting ATTR_SECURITY_ENABLE with the SAB state"); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_SECURITY_ENABLE, FAPI_SYSTEM, l_read_1)); } //read_scratch1_reg { - if ( l_read_scratch8.getBit<0>() ) - { - FAPI_DBG("Reading Scratch_reg1"); - //Getting SCRATCH_REGISTER_1 register value - FAPI_TRY(fapi2::getScom(i_target_chip, PERV_SCRATCH_REGISTER_1_SCOM, - l_read_scratch_reg)); //l_read_scratch_reg = PIB.SCRATCH_REGISTER_1 - - l_read_scratch_reg.extract<0, 6>(l_read_1); - l_read_scratch_reg.extract<8, 24>(l_read_5); - - FAPI_DBG("Setting up ATTR_EQ_GARD, ATTR_EC_GARD"); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_EQ_GARD, i_target_chip, l_read_1)); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_EC_GARD, i_target_chip, l_read_5)); - - l_read_1 = 0; - l_read_5 = 0; - } - else + if ( !l_read_scratch8.getBit<0>() ) { l_read_scratch_reg.flush<0>(); @@ -219,65 +193,7 @@ fapi2::ReturnCode p9_sbe_attr_setup(const uint8_t l_ob2_pll_bucket = 0; uint8_t l_ob3_pll_bucket = 0; - if ( l_read_scratch8.getBit<1>() ) - { - uint8_t l_ndl_meshctrl_setup = 0x0; - - FAPI_DBG("Reading Scratch_reg2"); - //Getting SCRATCH_REGISTER_2 register value - FAPI_TRY(fapi2::getScom(i_target_chip, PERV_SCRATCH_REGISTER_2_SCOM, - l_read_scratch_reg)); //l_read_scratch_reg = PIB.SCRATCH_REGISTER_2 - - l_read_scratch_reg.extractToRight<0, 16>(l_read_4); - - l_read_scratch_reg.extractToRight<ATTR_OB0_PLL_BUCKET_STARTBIT, ATTR_OB0_PLL_BUCKET_LENGTH>(l_ob0_pll_bucket); - l_read_scratch_reg.extractToRight<ATTR_OB1_PLL_BUCKET_STARTBIT, ATTR_OB1_PLL_BUCKET_LENGTH>(l_ob1_pll_bucket); - l_read_scratch_reg.extractToRight<ATTR_OB2_PLL_BUCKET_STARTBIT, ATTR_OB2_PLL_BUCKET_LENGTH>(l_ob2_pll_bucket); - l_read_scratch_reg.extractToRight<ATTR_OB3_PLL_BUCKET_STARTBIT, ATTR_OB3_PLL_BUCKET_LENGTH>(l_ob3_pll_bucket); - l_read_scratch_reg.extractToRight<ATTR_MC_PLL_BUCKET_STARTBIT, ATTR_MC_PLL_BUCKET_LENGTH>(l_read_1); - - // Workaround to handle backward compatibilty - // Old drivers will keep MBX OBUS PLL bucket value as zero. So - // change it to 1 to make old drivers compatible with new SBE - // image - if( 0 == l_ob0_pll_bucket ) - { - l_ob0_pll_bucket = 1; - } - - if( 0 == l_ob1_pll_bucket ) - { - l_ob1_pll_bucket = 1; - } - - if( 0 == l_ob2_pll_bucket ) - { - l_ob2_pll_bucket = 1; - } - - if( 0 == l_ob3_pll_bucket ) - { - l_ob3_pll_bucket = 1; - } - - FAPI_DBG("Setting up ATTR_I2C_BUS_DIV_REF"); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_I2C_BUS_DIV_REF, i_target_chip, l_read_4)); - - l_read_scratch_reg.extractToRight<16, 4>(l_ndl_meshctrl_setup); - l_ndl_meshctrl_setup = (~l_ndl_meshctrl_setup) & 0x0F; - FAPI_DBG("Setting up ATTR_NDL_MESHCTRL_SETUP"); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_NDL_MESHCTRL_SETUP, i_target_chip, l_ndl_meshctrl_setup)); - - FAPI_DBG("Setting up ATTR_MC_PLL_BUCKET"); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_MC_PLL_BUCKET, FAPI_SYSTEM, l_read_1)); - - FAPI_DBG("Setting up ATTR_OBX_PLL_BUCKET"); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_OB0_PLL_BUCKET, i_target_chip, l_ob0_pll_bucket)); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_OB1_PLL_BUCKET, i_target_chip, l_ob1_pll_bucket)); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_OB2_PLL_BUCKET, i_target_chip, l_ob2_pll_bucket)); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_OB3_PLL_BUCKET, i_target_chip, l_ob3_pll_bucket)); - } - else + if ( !l_read_scratch8.getBit<1>() ) { l_read_scratch_reg.flush<0>(); @@ -316,27 +232,7 @@ fapi2::ReturnCode p9_sbe_attr_setup(const //read_scratch3_reg { - uint8_t l_is_mpipl = 0; - uint8_t l_is_sp_mode = 0; - - if ( l_read_scratch8.getBit<2>() ) - { - FAPI_DBG("Reading Scratch_reg3"); - //Getting SCRATCH_REGISTER_3 register value - FAPI_TRY(fapi2::getScom(i_target_chip, PERV_SCRATCH_REGISTER_3_SCOM, - l_read_scratch_reg)); //l_read_scratch_reg = PIB.SCRATCH_REGISTER_3 - - l_read_scratch_reg.extractToRight<2, 1>(l_is_mpipl); - - FAPI_DBG("Setting up ATTR_IS_MPIPL"); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_IS_MPIPL, FAPI_SYSTEM, l_is_mpipl)); - - l_read_scratch_reg.extractToRight<3, 1>(l_is_sp_mode); - - FAPI_DBG("Setting up ATTR_IS_SP_MODE"); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_IS_SP_MODE, i_target_chip, l_is_sp_mode)); - } - else + if ( !l_read_scratch8.getBit<2>() ) { l_read_scratch_reg.flush<0>(); @@ -364,39 +260,7 @@ fapi2::ReturnCode p9_sbe_attr_setup(const uint8_t l_nest_mem_x_o_pci_bypass = 0; uint8_t l_attr_obus_ratio = 0; - if ( l_read_scratch8.getBit<3>() ) - { - FAPI_DBG("Reading Scratch_Reg4"); - //Getting SCRATCH_REGISTER_4 register value - FAPI_TRY(fapi2::getScom(i_target_chip, PERV_SCRATCH_REGISTER_4_SCOM, - l_read_scratch_reg)); //l_read_scratch_reg = PIB.SCRATCH_REGISTER_4 - - l_read_scratch_reg.extractToRight<0, 16>(l_read_4); - l_read_scratch_reg.extractToRight<16, 1>(l_cp_filter_bypass); - l_read_scratch_reg.extractToRight<17, 1>(l_ss_filter_bypass); - l_read_scratch_reg.extractToRight<18, 1>(l_io_filter_bypass); - l_read_scratch_reg.extractToRight<19, 1>(l_dpll_bypass); - l_read_scratch_reg.extractToRight<20, 1>(l_nest_mem_x_o_pci_bypass); - l_read_scratch_reg.extractToRight<ATTR_OBUS_RATIO_VALUE_BIT, 1>(l_attr_obus_ratio); - l_read_scratch_reg.extractToRight<ATTR_NEST_PLL_BUCKET_STARTBIT, ATTR_NEST_PLL_BUCKET_LENGTH>(l_read_1); - - FAPI_DBG("Setting up PLL bypass attributes"); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_CP_FILTER_BYPASS, i_target_chip, l_cp_filter_bypass)); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_SS_FILTER_BYPASS, i_target_chip, l_ss_filter_bypass)); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_IO_FILTER_BYPASS, i_target_chip, l_io_filter_bypass)); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_DPLL_BYPASS, i_target_chip, l_dpll_bypass)); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_NEST_MEM_X_O_PCI_BYPASS, i_target_chip, l_nest_mem_x_o_pci_bypass)); - FAPI_DBG("Setting up ATTR_BOOT_FREQ_MULT, ATTR_NEST_PLL_BUCKET"); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_BOOT_FREQ_MULT, i_target_chip, l_read_4)); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_NEST_PLL_BUCKET, FAPI_SYSTEM, l_read_1)); - - FAPI_DBG("Setting up ATTR_OBUS_RATIO_VALUE"); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_OBUS_RATIO_VALUE, i_target_chip, l_attr_obus_ratio)); - - l_read_1 = 0; - l_read_4 = 0; - } - else + if ( !l_read_scratch8.getBit<3>() ) { l_read_scratch_reg.flush<0>(); @@ -449,7 +313,7 @@ fapi2::ReturnCode p9_sbe_attr_setup(const uint8_t l_mc_sync_mode = 0; uint8_t l_slow_pci_ref_clock = 0; - if ( l_read_scratch8.getBit<4>() ) + if( l_read_scratch8.getBit<4>() ) { FAPI_DBG("Reading Scratch_reg5"); //Getting SCRATCH_REGISTER_5 register value @@ -465,47 +329,8 @@ fapi2::ReturnCode p9_sbe_attr_setup(const l_system_ipl_phase = fapi2::ENUM_ATTR_SYSTEM_IPL_PHASE_HB_IPL; } - l_read_scratch_reg.extract<1, 1, 7>(l_force_all_cores); - - if (l_read_scratch_reg.getBit<2>()) - { - l_risk_level = fapi2::ENUM_ATTR_RISK_LEVEL_TRUE; - } - else - { - l_risk_level = fapi2::ENUM_ATTR_RISK_LEVEL_FALSE; - } - - if (l_read_scratch_reg.getBit<3>()) - { - l_disable_hbbl_vectors = fapi2::ENUM_ATTR_DISABLE_HBBL_VECTORS_TRUE; - } - else - { - l_disable_hbbl_vectors = fapi2::ENUM_ATTR_DISABLE_HBBL_VECTORS_FALSE; - } - - l_read_scratch_reg.extract<4, 1, 7>(l_mc_sync_mode); - - if (l_read_scratch_reg.getBit<ATTR_SLOW_PCI_REF_CLOCK_BIT>()) - { - l_slow_pci_ref_clock = fapi2::ENUM_ATTR_DD1_SLOW_PCI_REF_CLOCK_NORMAL; - } - else - { - l_slow_pci_ref_clock = fapi2::ENUM_ATTR_DD1_SLOW_PCI_REF_CLOCK_SLOW; - } - - l_read_scratch_reg.extract<12, 20, 0>(l_pll_mux); - - FAPI_DBG("Setting up SYSTEM_IPL_PHASE, RISK_LEVEL, SYS_FORCE_ALL_CORES"); + FAPI_DBG("Setting up SYSTEM_IPL_PHASE"); FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_SYSTEM_IPL_PHASE, FAPI_SYSTEM, l_system_ipl_phase)); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_SYS_FORCE_ALL_CORES, FAPI_SYSTEM, l_force_all_cores)); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_RISK_LEVEL, FAPI_SYSTEM, l_risk_level)); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_DISABLE_HBBL_VECTORS, FAPI_SYSTEM, l_disable_hbbl_vectors)); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_MC_SYNC_MODE, i_target_chip, l_mc_sync_mode)); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_DD1_SLOW_PCI_REF_CLOCK, FAPI_SYSTEM, l_slow_pci_ref_clock)); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_CLOCK_PLL_MUX, i_target_chip, l_pll_mux)); } else { @@ -596,61 +421,7 @@ fapi2::ReturnCode p9_sbe_attr_setup(const { uint8_t l_pump_mode; - if ( l_read_scratch8.getBit<5>() ) - { - FAPI_DBG("Reading Scratch_reg6"); - //Getting SCRATCH_REGISTER_6 register value - FAPI_TRY(fapi2::getScom(i_target_chip, PERV_SCRATCH_REGISTER_6_SCOM, - l_read_scratch_reg)); //l_read_scratch_reg = PIB.SCRATCH_REGISTER_6 - - l_read_1 = 0; - sbe_slave_chip = l_read_scratch_reg.getBit<24>(); - - if ( !sbe_slave_chip ) // 0b0 == master - { - FAPI_DBG("Reading DEVICE_ID_REG value"); - FAPI_TRY(fapi2::getScom(i_target_chip, PERV_DEVICE_ID_REG, l_read_device_reg)); - - if (!l_read_device_reg.getBit<40>()) - { - l_read_1.setBit<7>(); - } - } - - if (l_read_scratch_reg.getBit<ATTR_PUMP_CHIP_IS_GROUP>()) - { - l_pump_mode = fapi2::ENUM_ATTR_PROC_FABRIC_PUMP_MODE_CHIP_IS_GROUP; - } - else - { - l_pump_mode = fapi2::ENUM_ATTR_PROC_FABRIC_PUMP_MODE_CHIP_IS_NODE; - } - - l_read_scratch_reg.extractToRight<26, 3>(l_read_2); - l_read_scratch_reg.extractToRight<29, 3>(l_read_3); - - FAPI_DBG("Setting up PUMP MODE"); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_PROC_FABRIC_PUMP_MODE, - fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), - l_pump_mode)); - - FAPI_DBG("Setting up MASTER_CHIP, FABRIC_GROUP_ID and CHIP_ID"); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_PROC_SBE_MASTER_CHIP, i_target_chip, - l_read_1)); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_PROC_FABRIC_GROUP_ID, i_target_chip, - l_read_2)); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_PROC_FABRIC_CHIP_ID, i_target_chip, - l_read_3)); - - l_read_scratch_reg.extractToRight<17, 3>(l_read_2); - l_read_scratch_reg.extractToRight<20, 3>(l_read_3); - - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_PROC_EFF_FABRIC_GROUP_ID, i_target_chip, - l_read_2)); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_PROC_EFF_FABRIC_CHIP_ID, i_target_chip, - l_read_3)); - } - else + if ( !l_read_scratch8.getBit<5>() ) { l_read_scratch_reg.flush<0>(); diff --git a/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml index 15cabe12..850cb305 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml @@ -193,7 +193,6 @@ SLOW = 0x01 </enum> <platInit/> - <writeable/> </attribute> <!-- ********************************************************************** --> <attribute> @@ -291,7 +290,6 @@ CHIP_IS_GROUP = 0x02 </enum> <platInit/> - <writeable/> </attribute> <!-- ********************************************************************** --> <attribute> @@ -421,10 +419,6 @@ </description> <valueType>uint8</valueType> <platInit/> - <!-- TODO: Story 155081 - Not supposed to be writeable, PPE needs to resolve this issue in - p9_sbe_attr_setup.C --> - <writeable/> </attribute> <!-- ********************************************************************** --> <attribute> @@ -438,10 +432,6 @@ </description> <valueType>uint8</valueType> <platInit/> - <!-- TODO: Story 155081 - Not supposed to be writeable, PPE needs to resolve this issue in - p9_sbe_attr_setup.C --> - <writeable/> </attribute> <!-- ********************************************************************** --> <attribute> @@ -454,10 +444,6 @@ </description> <valueType>uint8</valueType> <platInit/> - <!-- TODO: Story 155081 - Not supposed to be writeable, PPE needs to resolve this issue in - p9_sbe_attr_setup.C --> - <writeable/> </attribute> <!-- ********************************************************************** --> <attribute> @@ -781,11 +767,8 @@ <valueType>uint8</valueType> <enum>HB_IPL = 0x1,HB_RUNTIME = 0x2,CACHE_CONTAINED = 0x4,CHIP_CONTAINED = 0x8,NONHB_IPL = 0x10</enum> <persistRuntime/> - <platInit/> - <!-- TODO: Story 155081 - Not supposed to be writeable, PPE needs to resolve this issue in - p9_sbe_attr_setup.C --> <writeable/> + <platInit/> </attribute> <!-- ********************************************************************** --> <attribute> @@ -800,10 +783,6 @@ TRUE = 0x1 </enum> <platInit/> - <!-- TODO: Story 155081 - Not supposed to be writeable, PPE needs to resolve this issue in - sberegaccess.C --> - <writeable/> <initToZero/> </attribute> <!-- ********************************************************************** --> diff --git a/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_load_bootloader_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_load_bootloader_attributes.xml index a69a44f8..0fd5d891 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_load_bootloader_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_load_bootloader_attributes.xml @@ -107,7 +107,6 @@ <valueType>uint64</valueType> <persistRuntime/> <platInit/> - <writeable/> <initToZero/> </attribute> </attributes> diff --git a/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml index 06009e70..2a8e04d1 100755 --- a/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml @@ -34,10 +34,6 @@ <description>setup clock mux settings</description> <valueType>uint32</valueType> <platInit/> - <!-- TODO: Story 155081 - Not supposed to be writeable, PPE needs to resolve this issue in - p9_sbe_attr_setup.C --> - <writeable/> </attribute> <attribute> @@ -55,7 +51,6 @@ <valueType>uint16</valueType> <persistRuntime/> <platInit/> - <writeable/> </attribute> <attribute> @@ -65,7 +60,6 @@ <valueType>uint8</valueType> <persistRuntime/> <platInit/> - <writeable/> </attribute> <attribute> @@ -75,7 +69,6 @@ <valueType>uint32</valueType> <persistRuntime/> <platInit/> - <writeable/> </attribute> <attribute> @@ -106,7 +99,6 @@ <enum>FSP_LESS = 0x0,FSP = 0x1</enum> <persistRuntime/> <platInit/> - <writeable/> </attribute> <attribute> @@ -137,7 +129,6 @@ <valueType>uint8</valueType> <persistRuntime/> <platInit/> - <writeable/> </attribute> <attribute> @@ -147,7 +138,6 @@ <valueType>uint8</valueType> <persistRuntime/> <platInit/> - <writeable/> </attribute> <attribute> @@ -157,7 +147,6 @@ <valueType>uint8</valueType> <persistRuntime/> <platInit/> - <writeable/> </attribute> <attribute> @@ -167,7 +156,6 @@ <valueType>uint8</valueType> <persistRuntime/> <platInit/> - <writeable/> </attribute> <attribute> @@ -177,7 +165,6 @@ <valueType>uint8</valueType> <persistRuntime/> <platInit/> - <writeable/> </attribute> <attribute> @@ -196,7 +183,6 @@ <valueType>uint16</valueType> <persistRuntime/> <platInit/> - <writeable/> </attribute> <attribute> @@ -208,7 +194,6 @@ <enum>FALSE = 0x0,TRUE = 0x1</enum> <persistRuntime/> <platInit/> - <writeable/> </attribute> <attribute> @@ -220,7 +205,6 @@ <enum>FALSE = 0x0,TRUE = 0x1</enum> <persistRuntime/> <platInit/> - <writeable/> </attribute> <attribute> @@ -239,7 +223,6 @@ <valueType>uint32</valueType> <persistRuntime/> <platInit/> - <writeable/> </attribute> <attribute> @@ -384,7 +367,6 @@ <enum>FALSE = 0x0,TRUE = 0x1</enum> <persistRuntime/> <platInit/> - <writeable/> </attribute> <attribute> @@ -464,7 +446,6 @@ <valueType>uint8</valueType> <persistRuntime/> <platInit/> - <writeable/> </attribute> <attribute> @@ -474,7 +455,6 @@ </description> <valueType>uint8</valueType> <persistRuntime/> - <platInit/> <writeable/> </attribute> @@ -486,7 +466,6 @@ </description> <valueType>uint8</valueType> <persistRuntime/> - <platInit/> <writeable/> </attribute> @@ -496,7 +475,6 @@ <description>Holds the state of Security Access Bit (SAB)</description> <valueType>uint8</valueType> <platInit/> - <writeable/> </attribute> <attribute> @@ -512,7 +490,6 @@ </description> <valueType>uint8</valueType> <platInit/> - <writeable/> <initToZero/> </attribute> @@ -525,9 +502,6 @@ <initToZero/> </attribute> -<!-- TODO: Story 155081 - Not supposed to be writeable, PPE needs to resolve this issue in - p9_sbe_attr_setup.C --> <attribute> <id>ATTR_OBUS_RATIO_VALUE</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> @@ -538,7 +512,6 @@ <valueType>uint8</valueType> <persistRuntime/> <platInit/> - <writeable/> </attribute> <attribute> @@ -547,7 +520,6 @@ <description>Pibmem repair attribute 0</description> <valueType>uint64</valueType> <persistRuntime/> - <platInit/> <writeable/> </attribute> @@ -557,7 +529,6 @@ <description>Pibmem repair attribute 1</description> <valueType>uint64</valueType> <persistRuntime/> - <platInit/> <writeable/> </attribute> @@ -567,7 +538,6 @@ <description>Pibmem repair attribute 2</description> <valueType>uint64</valueType> <persistRuntime/> - <platInit/> <writeable/> </attribute> @@ -585,10 +555,6 @@ <description>To skip the locking sequence and check for lock of CP filter PLL</description> <valueType>uint8</valueType> <platInit/> - <!-- TODO: Story 155081 - Not supposed to be writeable, PPE needs to resolve this issue in - p9_sbe_attr_setup.C --> - <writeable/> </attribute> <attribute> @@ -597,10 +563,6 @@ <description>To skip the locking sequence and check for lock of SS filter PLL</description> <valueType>uint8</valueType> <platInit/> - <!-- TODO: Story 155081 - Not supposed to be writeable, PPE needs to resolve this issue in - p9_sbe_attr_setup.C --> - <writeable/> </attribute> <attribute> @@ -609,10 +571,6 @@ <description>To skip the locking sequence and check for lock of IO filter PLL</description> <valueType>uint8</valueType> <platInit/> - <!-- TODO: Story 155081 - Not supposed to be writeable, PPE needs to resolve this issue in - p9_sbe_attr_setup.C --> - <writeable/> </attribute> <attribute> @@ -621,10 +579,6 @@ <description>Skip locking sequence and check for lock of DPLL</description> <valueType>uint8</valueType> <platInit/> - <!-- TODO: Story 155081 - Not supposed to be writeable, PPE needs to resolve this issue in - p9_sbe_attr_setup.C --> - <writeable/> </attribute> <attribute> @@ -633,10 +587,6 @@ <description>Skip the locking sequence and check for lock of NEST/MEM/XBUS/OBUS/PCI PLLs</description> <valueType>uint8</valueType> <platInit/> - <!-- TODO: Story 155081 - Not supposed to be writeable, PPE needs to resolve this issue in - p9_sbe_attr_setup.C --> - <writeable/> </attribute> <attribute> @@ -675,7 +625,6 @@ <description>System Configurtion information - 1 indicates a chip present</description> <valueType>uint64</valueType> <platInit/> - <writeable/> </attribute> <attribute> @@ -784,7 +733,6 @@ <valueType>uint8</valueType> <persistRuntime/> <platInit/> - <writeable/> </attribute> </attributes> diff --git a/src/sbefw/sbecmdgeneric.C b/src/sbefw/sbecmdgeneric.C index 1e0655aa..1eef3b6d 100644 --- a/src/sbefw/sbecmdgeneric.C +++ b/src/sbefw/sbecmdgeneric.C @@ -351,7 +351,7 @@ uint32_t sbeSetSystemFabricMap( uint8_t *i_pArg ) SBE::higher32BWord(l_sysFabricMap), SBE::lower32BWord(l_sysFabricMap)); - FAPI_ATTR_SET(fapi2::ATTR_SBE_SYS_CONFIG, + PLAT_ATTR_INIT(fapi2::ATTR_SBE_SYS_CONFIG, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), l_sysFabricMap); }while(0); diff --git a/src/sbefw/sbecmdiplcontrol.C b/src/sbefw/sbecmdiplcontrol.C index cfa595ce..cf9d251e 100644 --- a/src/sbefw/sbecmdiplcontrol.C +++ b/src/sbefw/sbecmdiplcontrol.C @@ -807,7 +807,7 @@ ReturnCode istepWithCore( sbeIstepHwp_t i_hwp) } // Only continue in case of istep4 && fuse core mode if(!( (fuseMode) && - (SbeRegAccess::theSbeRegAccess().getSbeMajorIstepNumber() == + (SbeRegAccess::theSbeRegAccess().getSbeMajorIstepNumber() == SBE_ISTEP4) ) ) { break; @@ -884,7 +884,7 @@ ReturnCode istepLoadBootLoader( sbeIstepHwp_t i_hwp) // Update the ATTR_SBE_ADDR_KEY_STASH_ADDR before calling the bootloader, // since it is going to access these data from inside. uint64_t addr = SBE_GLOBAL->sbeKeyAddrPair.fetchStashAddrAttribute(); - FAPI_ATTR_SET(fapi2::ATTR_SBE_ADDR_KEY_STASH_ADDR, sysTgt, addr); + PLAT_ATTR_INIT(fapi2::ATTR_SBE_ADDR_KEY_STASH_ADDR, sysTgt, addr); SBE_EXEC_HWP(rc, p9_sbe_load_bootloader, proc, exTgt, hbblSection->iv_size, getSectionAddr(hbblSection)) if(rc != FAPI2_RC_SUCCESS) @@ -1386,8 +1386,8 @@ ReturnCode istepMpiplSetFunctionalState( sbeIstepHwp_t i_hwp ) "ATTR_EC_GARD [0x%08X]", l_eqMask, l_ecMask); - FAPI_ATTR_SET(fapi2::ATTR_EQ_GARD, proc, l_eqMask); - FAPI_ATTR_SET(fapi2::ATTR_EC_GARD, proc, l_ecMask); + PLAT_ATTR_INIT(fapi2::ATTR_EQ_GARD, proc, l_eqMask); + PLAT_ATTR_INIT(fapi2::ATTR_EC_GARD, proc, l_ecMask); // Apply the gard records rc = plat_ApplyGards(); @@ -1553,7 +1553,7 @@ ReturnCode updatePhbFunctionalState( void ) uint8_t pci_id = 0; uint8_t phbPerPciCnt = 0; uint64_t data = 0; - + FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, phbTgt, phb_id); if(phb_id == 1 || phb_id == 2) { diff --git a/src/sbefw/sbemain.C b/src/sbefw/sbemain.C index 63707b90..bb0d4f43 100644 --- a/src/sbefw/sbemain.C +++ b/src/sbefw/sbemain.C @@ -301,6 +301,16 @@ uint32_t main(int argc, char **argv) break; } + fapiRc = fapi2::plat_AttrInit(); + if(fapiRc != fapi2::FAPI2_RC_SUCCESS) + { + SBE_ERROR(SBE_FUNC"plat_AttrInit failed"); + (void)SbeRegAccess::theSbeRegAccess(). + stateTransition(SBE_FAILURE_EVENT); + // Hard Reset SBE to recover + break; + } + if(SbeRegAccess::theSbeRegAccess().init()) { SBE_ERROR(SBE_FUNC"Failed to initialize SbeRegAccess."); diff --git a/src/sbefw/sberegaccess.C b/src/sbefw/sberegaccess.C index 0550fa28..7ca23291 100644 --- a/src/sbefw/sberegaccess.C +++ b/src/sbefw/sberegaccess.C @@ -320,7 +320,7 @@ uint32_t SbeRegAccess::setMpIplMode(const bool i_set) uint32_t rc = 0; uint8_t l_set = i_set; iv_mpiplMode = i_set; - FAPI_ATTR_SET(ATTR_IS_MPIPL, Target<TARGET_TYPE_SYSTEM>(), l_set); + PLAT_ATTR_INIT(ATTR_IS_MPIPL, Target<TARGET_TYPE_SYSTEM>(), l_set); rc = putscom_abs(PERV_SCRATCH_REGISTER_3_SCOM, iv_mbx3); if(rc) { |