diff options
author | Anusha Reddy Rangareddygari <anusrang@in.ibm.com> | 2016-09-19 14:44:16 +0200 |
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committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2016-09-26 14:38:47 -0400 |
commit | 1359652e4f8a9aa8cff3583b120ca33858cabf8f (patch) | |
tree | e568fc66188315d2ccc2a5a346c3915d94f72e01 | |
parent | 2a0cbf361398720c379c5d1c2c428c5b5e191cd4 (diff) | |
download | talos-sbe-1359652e4f8a9aa8cff3583b120ca33858cabf8f.tar.gz talos-sbe-1359652e4f8a9aa8cff3583b120ca33858cabf8f.zip |
FFDC Updates
Change-Id: I75faf871652e5320889961516b203ad5356c7843
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29885
Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Deepak Kodihalli <dkodihal@in.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29886
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
12 files changed, 945 insertions, 161 deletions
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_perv_sbe_cmn.C b/src/import/chips/p9/procedures/hwp/perv/p9_perv_sbe_cmn.C index a15db407..d205be95 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_perv_sbe_cmn.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_perv_sbe_cmn.C @@ -206,7 +206,11 @@ fapi2::ReturnCode p9_perv_sbe_cmn_array_init_module(const FAPI_DBG("Loop Count :%d", l_timeout); FAPI_ASSERT(l_timeout > 0, - fapi2::SBE_ARRAYINIT_POLL_THRESHOLD_ERR(), + fapi2::SBE_ARRAYINIT_POLL_THRESHOLD_ERR() + .set_TARGET_CHIPLET(i_target_chiplets) + .set_PERV_CPLT_STAT0(l_data64) + .set_LOOP_COUNT(l_timeout) + .set_HW_DELAY(P9_OPCG_DONE_ARRAYINIT_HW_NS_DELAY), "ERROR:OPCG DONE BIT NOT SET"); //Getting CPLT_STAT0 register value @@ -218,6 +222,9 @@ fapi2::ReturnCode p9_perv_sbe_cmn_array_init_module(const FAPI_DBG("Checking sram abist done"); FAPI_ASSERT(l_read_reg.getBit<0>() == 1, fapi2::SRAM_ABIST_DONE_BIT_ERR() + .set_TARGET_CHIPLET(i_target_chiplets) + .set_PERV_CPLT_STAT(l_read_reg) + .set_SELECT_SRAM(i_select_sram) .set_READ_ABIST_DONE(l_abist_check), "ERROR:SRAM_ABIST_DONE_BIT_NOT_SET"); } @@ -227,6 +234,9 @@ fapi2::ReturnCode p9_perv_sbe_cmn_array_init_module(const FAPI_DBG("Checking edram abist done"); FAPI_ASSERT(l_read_reg.getBit<1>() == 1, fapi2::EDRAM_ABIST_DONE_BIT_ERR() + .set_TARGET_CHIPLET(i_target_chiplets) + .set_PERV_CPLT_STAT(l_read_reg) + .set_SELECT_EDRAM(i_select_edram) .set_READ_ABIST_DONE(l_abist_check), "ERROR:EDRAM_ABIST_DONE_BIT_NOT_SET"); } @@ -455,7 +465,11 @@ fapi2::ReturnCode p9_perv_sbe_cmn_scan0_module(const FAPI_DBG("Loop Count :%d", l_timeout); FAPI_ASSERT(l_timeout > 0, - fapi2::SBE_SCAN0_DONE_POLL_THRESHOLD_ERR(), + fapi2::SBE_SCAN0_DONE_POLL_THRESHOLD_ERR() + .set_TARGET_CHIPLET(i_target_chiplets) + .set_PERV_CPLT_STAT0(l_data64) + .set_LOOP_COUNT(l_timeout) + .set_HW_DELAY(P9_OPCG_DONE_SCAN0_HW_NS_DELAY), "ERROR:OPCG DONE BIT NOT SET"); //os0m_poll_done diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.C index e5da6efa..0b51aef1 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.C @@ -58,23 +58,23 @@ enum P9_SBE_CHIPLET_PLL_SETUP_Private_Constants }; static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_check_pci_pll_lock( - const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip); + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet); static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_check_pll_lock( - const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip); + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet); static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_function( const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, const bool i_bypass); static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_mc_dcc_bypass( - const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip); + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet); static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_mc_pdly_bypass( const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet); static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_pll_reset( - const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip); + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet); static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_pll_test_enable( const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet); @@ -225,21 +225,24 @@ fapi_try_exit: /// @brief check pll lock for pcie chiplet /// -/// @param[in] i_target_chip Reference to TARGET_TYPE_PERV target +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target /// @return FAPI2_RC_SUCCESS if success, else error code. static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_check_pci_pll_lock( - const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip) + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet) { fapi2::buffer<uint64_t> l_read_reg; + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_chip = i_target_chiplet.getParent<fapi2::TARGET_TYPE_PROC_CHIP>(); FAPI_INF("p9_sbe_chiplet_pll_setup_check_pci_pll_lock: Entering ..."); FAPI_DBG("Check PLL lock"); //Getting PLL_LOCK_REG register value - FAPI_TRY(fapi2::getScom(i_target_chip, PERV_PLL_LOCK_REG, + FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_PLL_LOCK_REG, l_read_reg)); //l_read_reg = PLL_LOCK_REG FAPI_ASSERT(l_read_reg.getBit<0>() == 1 && l_read_reg.getBit<1>() == 1, fapi2::PLL_LOCK_ERR() + .set_TARGET_CHIPLET(i_target_chiplet) + .set_TARGET_CHIP(l_chip) .set_PLL_READ(l_read_reg), "ERROR:PLL LOCK NOT SET"); @@ -252,21 +255,24 @@ fapi_try_exit: /// @brief check pll lock for OB,XB,MC /// -/// @param[in] i_target_chip Reference to TARGET_TYPE_PERV target +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target /// @return FAPI2_RC_SUCCESS if success, else error code. static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_check_pll_lock( - const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip) + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet) { fapi2::buffer<uint64_t> l_read_reg; + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_chip = i_target_chiplet.getParent<fapi2::TARGET_TYPE_PROC_CHIP>(); FAPI_INF("p9_sbe_chiplet_pll_setup_check_pll_lock: Entering ..."); FAPI_DBG("Check PLL lock"); //Getting PLL_LOCK_REG register value - FAPI_TRY(fapi2::getScom(i_target_chip, PERV_PLL_LOCK_REG, + FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_PLL_LOCK_REG, l_read_reg)); //l_read_reg = PLL_LOCK_REG FAPI_ASSERT(l_read_reg.getBit<0>() == 1 , fapi2::PLL_LOCK_ERR() + .set_TARGET_CHIPLET(i_target_chiplet) + .set_TARGET_CHIP(l_chip) .set_PLL_READ(l_read_reg), "ERROR:PLL LOCK NOT SET"); @@ -322,7 +328,7 @@ fapi_try_exit: /// @param[in] i_target_chip Reference to TARGET_TYPE_PERV target /// @return FAPI2_RC_SUCCESS if success, else error code. static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_mc_dcc_bypass( - const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip) + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet) { fapi2::buffer<uint64_t> l_data64; FAPI_INF("p9_sbe_chiplet_pll_setup_mc_dcc_bypass: Entering ..."); @@ -332,7 +338,7 @@ static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_mc_dcc_bypass( l_data64.flush<1>(); //NET_CTRL1.CLK_DCC_BYPASS_EN = 0 l_data64.clearBit<PERV_1_NET_CTRL1_CLK_DCC_BYPASS_EN>(); - FAPI_TRY(fapi2::putScom(i_target_chip, PERV_NET_CTRL1_WAND, l_data64)); + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL1_WAND, l_data64)); FAPI_INF("p9_sbe_chiplet_pll_setup_mc_dcc_bypass: Exiting ..."); @@ -370,7 +376,7 @@ fapi_try_exit: /// @param[in] i_target_chip Reference to TARGET_TYPE_PERV target /// @return FAPI2_RC_SUCCESS if success, else error code. static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_pll_reset( - const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip) + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet) { fapi2::buffer<uint64_t> l_data64; FAPI_INF("p9_sbe_chiplet_pll_setup_pll_reset: Entering ..."); @@ -379,7 +385,7 @@ static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_pll_reset( //Setting NET_CTRL0 register value l_data64.flush<1>(); l_data64.clearBit<PERV_1_NET_CTRL0_PLL_RESET>(); //NET_CTRL0.PLL_RESET = 0 - FAPI_TRY(fapi2::putScom(i_target_chip, PERV_NET_CTRL0_WAND, l_data64)); + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL0_WAND, l_data64)); fapi2::delay(NS_DELAY, SIM_CYCLE_DELAY); diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C index 7523181a..6941b2f6 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C @@ -120,7 +120,11 @@ fapi2::ReturnCode p9_sbe_common_align_chiplets(const FAPI_DBG("Loop Count :%d", l_timeout); FAPI_ASSERT(l_timeout > 0, - fapi2::CPLT_NOT_ALIGNED_ERR(), + fapi2::CPLT_NOT_ALIGNED_ERR() + .set_TARGET_CHIPLET(i_target_chiplets) + .set_PERV_CPLT_STAT0(l_data64) + .set_LOOP_COUNT(l_timeout) + .set_HW_DELAY(NS_DELAY), "ERROR:CHIPLET NOT ALIGNED"); FAPI_DBG("For all chiplets: disable alignement"); @@ -185,6 +189,7 @@ fapi2::ReturnCode p9_sbe_common_check_cc_status_function( FAPI_ASSERT(l_sl_clkregion_status == l_regions, fapi2::NEST_SL_ERR() + .set_TARGET_CHIPLET(i_target) .set_READ_CLK_SL(l_sl_clock_status), "Clock running for sl type not matching with expected values"); } @@ -198,6 +203,7 @@ fapi2::ReturnCode p9_sbe_common_check_cc_status_function( FAPI_ASSERT(l_sl_clkregion_status == l_regions, fapi2::NEST_SL_ERR() + .set_TARGET_CHIPLET(i_target) .set_READ_CLK_SL(l_sl_clock_status), "Clock running for sl type not matching with expected values"); } @@ -221,6 +227,7 @@ fapi2::ReturnCode p9_sbe_common_check_cc_status_function( FAPI_ASSERT(l_nsl_clkregion_status == l_regions, fapi2::NEST_NSL_ERR() + .set_TARGET_CHIPLET(i_target) .set_READ_CLK_NSL(l_nsl_clock_status), "Clock running for nsl type not matching with expected values"); } @@ -234,6 +241,7 @@ fapi2::ReturnCode p9_sbe_common_check_cc_status_function( FAPI_ASSERT(l_nsl_clkregion_status == l_regions, fapi2::NEST_NSL_ERR() + .set_TARGET_CHIPLET(i_target) .set_READ_CLK_NSL(l_nsl_clock_status), "Clock running for nsl type not matching with expected values"); } @@ -257,6 +265,7 @@ fapi2::ReturnCode p9_sbe_common_check_cc_status_function( FAPI_ASSERT(l_ary_clkregion_status == l_regions, fapi2::NEST_ARY_ERR() + .set_TARGET_CHIPLET(i_target) .set_READ_CLK_ARY(l_ary_clock_status), "Clock running for ary type not matching with expected values"); } @@ -270,6 +279,7 @@ fapi2::ReturnCode p9_sbe_common_check_cc_status_function( FAPI_ASSERT(l_ary_clkregion_status == l_regions, fapi2::NEST_ARY_ERR() + .set_TARGET_CHIPLET(i_target) .set_READ_CLK_ARY(l_ary_clock_status), "Clock running for ary type not matching with expected values"); } @@ -429,7 +439,11 @@ fapi2::ReturnCode p9_sbe_common_clock_start_stop(const FAPI_DBG("Loop Count after CPLT_OPCG_DONE_DC polling:%d", l_timeout); FAPI_ASSERT(l_timeout > 0, - fapi2::CPLT_OPCG_DONE_NOT_SET_ERR(), + fapi2::CPLT_OPCG_DONE_NOT_SET_ERR() + .set_TARGET_CHIPLET(i_target) + .set_PERV_CPLT_STAT0(l_data64) + .set_LOOP_COUNT(l_timeout) + .set_HW_DELAY(NS_DELAY), "ERROR:CHIPLET OPCG DONE NOT SET AFTER CLOCK START STOP CMD"); //To do do checking only for chiplets that dont have Master-slave mode enabled @@ -456,6 +470,7 @@ fapi2::ReturnCode p9_sbe_common_clock_start_stop(const FAPI_ASSERT(l_sl_clock_status == l_exp_sl_clock_status, fapi2::SL_ERR() + .set_TARGET_CHIPLET(i_target) .set_READ_CLK_SL(l_sl_clock_status), "CLOCK RUNNING STATUS FOR SL TYPE NOT MATCHING WITH EXPECTED VALUES"); @@ -468,6 +483,7 @@ fapi2::ReturnCode p9_sbe_common_clock_start_stop(const FAPI_ASSERT(l_nsl_clock_status == l_exp_nsl_clock_status, fapi2::NSL_ERR() + .set_TARGET_CHIPLET(i_target) .set_READ_CLK_NSL(l_nsl_clock_status), "CLOCK RUNNING STATUS IS NOT MATCHING WITH EXPECTED VALUE FOR NSL TYPE"); @@ -480,6 +496,7 @@ fapi2::ReturnCode p9_sbe_common_clock_start_stop(const FAPI_ASSERT(l_ary_clock_status == l_exp_ary_clock_status, fapi2::ARY_ERR() + .set_TARGET_CHIPLET(i_target) .set_READ_CLK_ARY(l_ary_clock_status), "CLOCK RUNNING STATUS IS NOT MATCHING WITH EXPECTED VALUE FOR ARRAY TYPE"); } diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_setup.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_setup.C index 6a25a858..9c10724b 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_setup.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_setup.C @@ -57,6 +57,9 @@ fapi2::ReturnCode p9_sbe_npll_setup(const fapi2::buffer<uint64_t> l_read_reg; uint8_t l_read_attr = 0; uint8_t l_nest_bypass = 0; + uint8_t l_attr_ss_filter = 0; + uint8_t l_attr_cp_filter = 0; + uint8_t l_attr_io_filter = 0; fapi2::buffer<uint64_t> l_data64_root_ctrl8; fapi2::buffer<uint64_t> l_data64_perv_ctrl0; FAPI_INF("p9_sbe_npll_setup: Entering ..."); @@ -66,12 +69,18 @@ fapi2::ReturnCode p9_sbe_npll_setup(const FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL8_SCOM, l_data64_root_ctrl8)); //l_data64_root_ctrl8 = PIB.ROOT_CTRL8 - - FAPI_DBG("Reading ATTR_SS_FILTER_BYPASS"); + FAPI_DBG("Reading ATTR_SS_FILTER_BYPASS, ATTR_CP_FILTER_BYPASS, ATTR_IO_FILTER_BYPASS"); FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SS_FILTER_BYPASS, i_target_chip, - l_read_attr)); + l_attr_ss_filter)); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CP_FILTER_BYPASS, i_target_chip, + l_attr_cp_filter)); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IO_FILTER_BYPASS, i_target_chip, + l_attr_io_filter)); + FAPI_DBG("SS,CP and IO filter configuration 1.ATTR_SS_FILTER_BYPASS: %#018lX 2.ATTR_CP_FILTER_BYPASS: %#018lX 3.ATTR_IO_FILTER_BYPASS: %#018lX", + l_attr_ss_filter, l_attr_cp_filter, l_attr_io_filter); + - if ( l_read_attr == 0x0 ) + if (l_attr_ss_filter == 0x0 ) { FAPI_DBG("Drop PLL test enable for Spread Spectrum PLL"); //Setting ROOT_CTRL8 register value @@ -96,6 +105,7 @@ fapi2::ReturnCode p9_sbe_npll_setup(const FAPI_ASSERT(l_read_reg.getBit<0>(), fapi2::SS_PLL_LOCK_ERR() + .set_MASTER_CHIP(i_target_chip) .set_SS_PLL_READ(l_read_reg), "ERROR:SS PLL LOCK NOT SET"); @@ -107,11 +117,7 @@ fapi2::ReturnCode p9_sbe_npll_setup(const l_data64_root_ctrl8)); } - FAPI_DBG("Reading ATTR_CP_FILTER_BYPASS"); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CP_FILTER_BYPASS, i_target_chip, - l_read_attr)); - - if ( l_read_attr == 0x0 ) + if ( l_attr_cp_filter == 0x0 ) { FAPI_DBG("Drop PLL test enable for CP Filter PLL"); //Setting ROOT_CTRL8 register value @@ -136,6 +142,7 @@ fapi2::ReturnCode p9_sbe_npll_setup(const FAPI_ASSERT(l_read_reg.getBit<1>(), fapi2::CP_FILTER_PLL_LOCK_ERR() + .set_MASTER_CHIP(i_target_chip) .set_CP_FILTER_PLL_READ(l_read_reg), "ERROR:CP FILTER PLL LOCK NOT SET"); @@ -147,11 +154,7 @@ fapi2::ReturnCode p9_sbe_npll_setup(const l_data64_root_ctrl8)); } - FAPI_DBG("Reading ATTR_IO_FILTER_BYPASS"); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IO_FILTER_BYPASS, i_target_chip, - l_read_attr)); - - if ( l_read_attr == 0x0 ) + if ( l_attr_io_filter == 0x0 ) { FAPI_DBG("Drop PLL test enable for IO Filter PLL"); //Setting ROOT_CTRL8 register value @@ -176,6 +179,7 @@ fapi2::ReturnCode p9_sbe_npll_setup(const FAPI_ASSERT(l_read_reg.getBit<2>(), fapi2::IO_FILTER_PLL_LOCK_ERR() + .set_MASTER_CHIP(i_target_chip) .set_IO_FILTER_PLL_READ(l_read_reg), "ERROR:IO FILTER PLL LOCK NOT SET"); @@ -234,7 +238,11 @@ fapi2::ReturnCode p9_sbe_npll_setup(const FAPI_ASSERT(l_read_reg.getBit<3>(), fapi2::NEST_PLL_ERR() - .set_NEST_PLL_READ(l_read_reg), + .set_MASTER_CHIP(i_target_chip) + .set_NEST_PLL_READ(l_read_reg) + .set_SS_FILTER_BYPASS_STATUS(l_attr_ss_filter) + .set_CP_FILTER_BYPASS_STATUS(l_attr_cp_filter) + .set_IO_FILTER_BYPASS_STATUS(l_attr_io_filter), "ERROR:NEST PLL LOCK NOT SET"); FAPI_DBG("Release PLL bypass2"); diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init3.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init3.C index 41801eb7..69b617f2 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init3.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init3.C @@ -218,9 +218,10 @@ fapi2::ReturnCode p9_sbe_tp_chiplet_init3(const FAPI_DBG("Loop Count :%d", l_timeout); - FAPI_ASSERT(l_timeout > 0, - fapi2::CALIBRATION_NOT_DONE(), - "Calibration not done, bit16 not set"); + if(!(l_timeout > 0)) + { + FAPI_DBG("Calibration not done, bit16 not set"); + } FAPI_INF("p9_sbe_tp_chiplet_init3: Exiting ..."); @@ -302,6 +303,7 @@ static fapi2::ReturnCode p9_sbe_tp_chiplet_init3_clock_test2( FAPI_ASSERT(l_read.getBit<21>() == 0 && l_read.getBit<28>() == 1, fapi2::MF_OSC_NOT_TOGGLE() + .set_MASTER_CHIP(i_target_chip) .set_READ_SNS1LTH(l_read), "MF oscillator not toggling"); @@ -312,6 +314,7 @@ static fapi2::ReturnCode p9_sbe_tp_chiplet_init3_clock_test2( FAPI_ASSERT(l_read.getBit<4>() == 0, fapi2::MF_OSC_ERR() + .set_MASTER_CHIP(i_target_chip) .set_READ_OSCERR_HOLD(l_read), "MF oscillator error active"); diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_switch_gears.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_switch_gears.C index 5c1159d5..4008db8c 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_switch_gears.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_switch_gears.C @@ -141,7 +141,10 @@ fapi2::ReturnCode p9_sbe_tp_switch_gears_check_magicnumber( FAPI_DBG("Loop Count :%d", l_timeout); FAPI_ASSERT(l_timeout > 0, - fapi2::BUS_STATUS_BUSY0(), + fapi2::I2C_BUS_STATUS_BUSY() + .set_MASTER_CHIP(i_target_chip) + .set_STATUS_REGISTER_B(l_data64) + .set_LOOP_COUNT(l_timeout), "ERROR:BUS_STSTUS_BUSY_0 NOT SET TO 0"); FAPI_DBG("Reading the value of DATA0TO7_REGISTER_B"); @@ -150,7 +153,11 @@ fapi2::ReturnCode p9_sbe_tp_switch_gears_check_magicnumber( l_read_reg)); //l_read_reg = PIB.DATA0TO7_REGISTER_B FAPI_ASSERT(l_read_reg == MAGIC_NUMBER, - fapi2::MAGIC_NUMBER_NOT_VALID(), + fapi2::MAGIC_NUMBER_NOT_VALID() + .set_MASTER_CHIP(i_target_chip) + .set_DATA0TO7_REGISTER_B(l_read_reg) + .set_MAGIC_NUMBER_VALUE(MAGIC_NUMBER) + .set_BACKUP_SEEPROM_ATTR(l_read_attr), "ERROR: Magic number not matching"); FAPI_INF("p9_sbe_tp_switch_gears_check_magicnumber: Exiting ..."); diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_perv_sbe_cmn_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_perv_sbe_cmn_errors.xml index 373ea617..b7e472d7 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_perv_sbe_cmn_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_perv_sbe_cmn_errors.xml @@ -29,29 +29,163 @@ <hwpErrors> <!-- ******************************************************************** --> <hwpError> - <sbeError/> - <rc>RC_SBE_SCAN0_DONE_POLL_THRESHOLD_ERR</rc> - <description>Timeout waiting for scan0 to complete , loop count expired that polls for OPCG_DONE</description> + <sbeError/> + <rc>RC_SBE_SCAN0_DONE_POLL_THRESHOLD_ERR</rc> + <description>Timeout waiting for scan0 to complete , loop count expired that polls for OPCG_DONE</description> + <ffdc>TARGET_CHIPLET</ffdc> + <collectRegisterFfdc> + <id>NET_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CPLT_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>OPCG_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CC_STATUS_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>ERROR_STATUS_OF_CC</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CC_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <ffdc>PERV_CPLT_STAT0</ffdc> + <ffdc>LOOP_COUNT</ffdc> + <ffdc>HW_DELAY</ffdc> </hwpError> <!-- ******************************************************************** --> <hwpError> - <sbeError/> - <rc>RC_SBE_ARRAYINIT_POLL_THRESHOLD_ERR</rc> - <description>Polling for OPCG_DONE for arrayInit reached threshold , count expired.</description> + <sbeError/> + <rc>RC_SBE_ARRAYINIT_POLL_THRESHOLD_ERR</rc> + <description>Polling for OPCG_DONE for arrayInit reached threshold , count expired.</description> + <ffdc>TARGET_CHIPLET</ffdc> + <collectRegisterFfdc> + <id>NET_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CPLT_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>OPCG_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CC_STATUS_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>ERROR_STATUS_OF_CC</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CC_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <ffdc>PERV_CPLT_STAT0</ffdc> + <ffdc>LOOP_COUNT</ffdc> + <ffdc>HW_DELAY</ffdc> </hwpError> <!-- ******************************************************************** --> <hwpError> - <sbeError/> - <rc>RC_SRAM_ABIST_DONE_BIT_ERR</rc> - <description>SRAM abist done bit is not set</description> - <ffdc>READ_ABIST_DONE</ffdc> + <sbeError/> + <rc>RC_SRAM_ABIST_DONE_BIT_ERR</rc> + <description>SRAM abist done bit is not set</description> + <ffdc>TARGET_CHIPLET</ffdc> + <collectRegisterFfdc> + <id>NET_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CPLT_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>OPCG_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CC_STATUS_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>ERROR_STATUS_OF_CC</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CC_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <ffdc>PERV_CPLT_STAT</ffdc> + <ffdc>SELECT_SRAM</ffdc> + <ffdc>READ_ABIST_DONE</ffdc> </hwpError> <!-- ******************************************************************** --> <hwpError> - <sbeError/> - <rc>RC_EDRAM_ABIST_DONE_BIT_ERR</rc> - <description>EDRAM abist done bit is not set</description> - <ffdc>READ_ABIST_DONE</ffdc> + <sbeError/> + <rc>RC_EDRAM_ABIST_DONE_BIT_ERR</rc> + <description>EDRAM abist done bit is not set</description> + <ffdc>TARGET_CHIPLET</ffdc> + <collectRegisterFfdc> + <id>NET_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CPLT_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>OPCG_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CC_STATUS_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>ERROR_STATUS_OF_CC</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CC_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <ffdc>PERV_CPLT_STAT</ffdc> + <ffdc>SELECT_EDRAM</ffdc> + <ffdc>READ_ABIST_DONE</ffdc> </hwpError> <!-- ******************************************************************** --> </hwpErrors> diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_chiplet_pll_setup_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_chiplet_pll_setup_errors.xml index 04d7f05e..f490d1a2 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_chiplet_pll_setup_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_chiplet_pll_setup_errors.xml @@ -25,14 +25,40 @@ <!-- This is an automatically generated file. --> <!-- File: p9_sbe_chiplet_pll_setup_errors.xml. --> <!-- Halt codes for p9_sbe_chiplet_pll_setup --> - <hwpErrors> - <!-- ******************************************************************** --> - <hwpError> - <sbeError/> - <rc>RC_PLL_LOCK_ERR</rc> - <description>PLL Lock Not set</description> - <ffdc>PLL_READ</ffdc> - </hwpError> - <!-- ******************************************************************** --> + <sbeTarget>TARGET_CHIP</sbeTarget> + <!-- ******************************************************************** --> + <hwpError> + <sbeError/> + <rc>RC_PLL_LOCK_ERR</rc> + <description>PLL Lock Not set</description> + <ffdc>TARGET_CHIPLET</ffdc> + <collectRegisterFfdc> + <id>NET_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CPLT_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>PLL_LOCK_REG</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>ROOT_CTRL_REGISTERS</id> + <target>TARGET_CHIP</target> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>PERV_CTRL_REGISTERS</id> + <target>TARGET_CHIP</target> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + </collectRegisterFfdc> + <ffdc>PLL_READ</ffdc> + </hwpError> + <!-- ******************************************************************** --> </hwpErrors> diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_common_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_common_errors.xml index 29c866d7..4b1a997d 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_common_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_common_errors.xml @@ -25,61 +25,514 @@ <!-- This is an automatically generated file. --> <!-- File: p9_sbe_common_errors.xml. --> <!-- Halt codes for p9_sbe_common --> - <hwpErrors> - <!-- ******************************************************************** --> - <hwpError> - <sbeError/> - <rc>RC_ARY_ERR</rc> - <description>ary_thold status not matching the expected value in clock start stop sequence</description> - <ffdc>READ_CLK_ARY</ffdc> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <sbeError/> - <rc>RC_NSL_ERR</rc> - <description>nsl_thold status not matching the expected value in clock start stop sequence</description> - <ffdc>READ_CLK_NSL</ffdc> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <sbeError/> - <rc>RC_SL_ERR</rc> - <description>sl_thold status not matching the expected value in clock start stop sequence</description> - <ffdc>READ_CLK_SL</ffdc> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <sbeError/> - <rc>RC_CPLT_NOT_ALIGNED_ERR</rc> - <description>Chiplet not aligned</description> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <sbeError/> - <rc>RC_CPLT_OPCG_DONE_NOT_SET_ERR</rc> - <description>Chiplet OPCG_DONE not set after clock start/stop command</description> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <sbeError/> - <rc>RC_NEST_ARY_ERR</rc> - <description>ary_thold status not matching the expected value in clock start stop sequence</description> - <ffdc>READ_CLK_ARY</ffdc> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <sbeError/> - <rc>RC_NEST_NSL_ERR</rc> - <description>nsl_thold status not matching the expected value in clock start stop sequence</description> - <ffdc>READ_CLK_NSL</ffdc> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <sbeError/> - <rc>RC_NEST_SL_ERR</rc> - <description>sl_thold status not matching the expected value in clock start stop sequence</description> - <ffdc>READ_CLK_SL</ffdc> - </hwpError> - <!-- ******************************************************************** --> + <!-- ******************************************************************** --> + <registerFfdc> + <id>ROOT_CTRL_REGISTERS_CFAM</id> + <cfamRegister>PERV_ROOT_CTRL0_FSI</cfamRegister> + <cfamRegister>PERV_ROOT_CTRL1_FSI</cfamRegister> + <cfamRegister>PERV_ROOT_CTRL2_FSI</cfamRegister> + <cfamRegister>PERV_ROOT_CTRL3_FSI</cfamRegister> + <cfamRegister>PERV_ROOT_CTRL4_FSI</cfamRegister> + <cfamRegister>PERV_ROOT_CTRL5_FSI</cfamRegister> + <cfamRegister>PERV_ROOT_CTRL6_FSI</cfamRegister> + <cfamRegister>PERV_ROOT_CTRL7_FSI</cfamRegister> + <cfamRegister>PERV_ROOT_CTRL8_FSI</cfamRegister> + </registerFfdc> + <registerFfdc> + <id>PERV_CTRL_REGISTERS_CFAM</id> + <cfamRegister>PERV_PERV_CTRL0_FSI</cfamRegister> + <cfamRegister>PERV_PERV_CTRL1_FSI</cfamRegister> + </registerFfdc> + <registerFfdc> + <id>FSI2PIB_STATUS</id> + <cfamRegister>PERV_FSI2PIB_STATUS_FSI</cfamRegister> + </registerFfdc> + <registerFfdc> + <id>OSC_SWITCH_SENSE_REGISTER_CFAM</id> + <cfamRegister>PERV_SNS1LTH_FSI</cfamRegister> + </registerFfdc> + <registerFfdc> + <id>OSC_SWITCH_SENSE_REGISTER</id> + <scomRegister>PERV_SNS1LTH_SCOM</scomRegister> + </registerFfdc> + <registerFfdc> + <id>OSC_ERROR_HOLD</id> + <scomRegister>PERV_TP_OSCERR_HOLD</scomRegister> + </registerFfdc> + <registerFfdc> + <id>ROOT_CTRL_REGISTERS</id> + <scomRegister>PERV_ROOT_CTRL0_SCOM</scomRegister> + <scomRegister>PERV_ROOT_CTRL1_SCOM</scomRegister> + <scomRegister>PERV_ROOT_CTRL2_SCOM</scomRegister> + <scomRegister>PERV_ROOT_CTRL3_SCOM</scomRegister> + <scomRegister>PERV_ROOT_CTRL4_SCOM</scomRegister> + <scomRegister>PERV_ROOT_CTRL5_SCOM</scomRegister> + <scomRegister>PERV_ROOT_CTRL6_SCOM</scomRegister> + <scomRegister>PERV_ROOT_CTRL7_SCOM</scomRegister> + <scomRegister>PERV_ROOT_CTRL8_SCOM</scomRegister> + </registerFfdc> + <registerFfdc> + <id>PERV_CTRL_REGISTERS</id> + <scomRegister>PERV_PERV_CTRL0_SCOM</scomRegister> + <scomRegister>PERV_PERV_CTRL1_SCOM</scomRegister> + </registerFfdc> + <registerFfdc> + <id>NET_CTRL_REGISTERS</id> + <scomRegister>PERV_NET_CTRL0</scomRegister> + <scomRegister>PERV_NET_CTRL1</scomRegister> + </registerFfdc> + <registerFfdc> + <id>CPLT_CTRL_REGISTERS</id> + <scomRegister>PERV_CPLT_CTRL0</scomRegister> + <scomRegister>PERV_CPLT_CTRL1</scomRegister> + </registerFfdc> + <registerFfdc> + <id>CPLT_CONFIG_REGISTERS</id> + <scomRegister>PERV_CPLT_CONF0</scomRegister> + <scomRegister>PERV_CPLT_CONF1</scomRegister> + </registerFfdc> + <registerFfdc> + <id>OTHER_CPLT_REGISTERS</id> + <scomRegister>PERV_CPLT_STAT0</scomRegister> + <scomRegister>PERV_CPLT_MASK0</scomRegister> + </registerFfdc> + <registerFfdc> + <id>PLL_LOCK_REG</id> + <scomRegister>PERV_PLL_LOCK_REG</scomRegister> + </registerFfdc> + <registerFfdc> + <id>I2C_REGISTERS</id> + <scomRegister>PU_CONTROL_REGISTER_B</scomRegister> + <scomRegister>PU_STATUS_REGISTER_B</scomRegister> + <scomRegister>PU_COMMAND_REGISTER_B</scomRegister> + <scomRegister>PU_MODE_REGISTER_B</scomRegister> + <scomRegister>PU_WATER_MARK_REGISTER_B</scomRegister> + <scomRegister>PU_INTERRUPT_MASK_REGISTER_READ_B</scomRegister> + <scomRegister>PU_INTERRUPT_COND_B</scomRegister> + <scomRegister>PU_INTERRUPTS_B</scomRegister> + <scomRegister>PU_STATUS_REGISTER_ENGINE_B</scomRegister> + <scomRegister>PU_EXTENDED_STATUS_B</scomRegister> + <scomRegister>PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_B</scomRegister> + <scomRegister>PU_I2C_BUSY_REGISTER_B</scomRegister> + </registerFfdc> + <registerFfdc> + <id>OPCG_CTRL_REGISTERS</id> + <scomRegister>PERV_OPCG_ALIGN</scomRegister> + <scomRegister>PERV_OPCG_REG0</scomRegister> + <scomRegister>PERV_OPCG_REG1</scomRegister> + <scomRegister>PERV_OPCG_REG2</scomRegister> + </registerFfdc> + <registerFfdc> + <id>CC_STATUS_REGISTERS</id> + <scomRegister>PERV_SCAN_REGION_TYPE</scomRegister> + <scomRegister>PERV_CLK_REGION</scomRegister> + <scomRegister>PERV_CLOCK_STAT_SL</scomRegister> + <scomRegister>PERV_CLOCK_STAT_NSL</scomRegister> + <scomRegister>PERV_CLOCK_STAT_ARY</scomRegister> + <scomRegister>PERV_BIST</scomRegister> + </registerFfdc> + <registerFfdc> + <id>ERROR_STATUS_OF_CC</id> + <scomRegister>PERV_ERROR_STATUS</scomRegister> + </registerFfdc> + <registerFfdc> + <id>CC_REGISTERS</id> + <scomRegister>PERV_XSTOP1</scomRegister> + <scomRegister>PERV_XSTOP2</scomRegister> + <scomRegister>PERV_XSTOP3</scomRegister> + <scomRegister>PERV_OPCG_CAPT1</scomRegister> + <scomRegister>PERV_OPCG_CAPT2</scomRegister> + <scomRegister>PERV_OPCG_CAPT3</scomRegister> + <scomRegister>PERV_DBG_CBS_CC</scomRegister> + </registerFfdc> + <!-- ******************************************************************** --> + <hwpError> + <sbeError/> + <rc>RC_ARY_ERR</rc> + <description>ary_thold status not matching the expected value in clock start stop sequence</description> + <ffdc>TARGET_CHIPLET</ffdc> + <collectRegisterFfdc> + <id>NET_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CPLT_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CPLT_CONFIG_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>OTHER_CPLT_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>OPCG_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CC_STATUS_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>ERROR_STATUS_OF_CC</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CC_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <ffdc>READ_CLK_ARY</ffdc> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <sbeError/> + <rc>RC_NSL_ERR</rc> + <description>nsl_thold status not matching the expected value in clock start stop sequence</description> + <ffdc>TARGET_CHIPLET</ffdc> + <collectRegisterFfdc> + <id>NET_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CPLT_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CPLT_CONFIG_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>OTHER_CPLT_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>OPCG_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CC_STATUS_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>ERROR_STATUS_OF_CC</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CC_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <ffdc>READ_CLK_NSL</ffdc> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <sbeError/> + <rc>RC_SL_ERR</rc> + <description>sl_thold status not matching the expected value in clock start stop sequence</description> + <ffdc>TARGET_CHIPLET</ffdc> + <collectRegisterFfdc> + <id>NET_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CPLT_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CPLT_CONFIG_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>OTHER_CPLT_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>OPCG_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CC_STATUS_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>ERROR_STATUS_OF_CC</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CC_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <ffdc>READ_CLK_SL</ffdc> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <sbeError/> + <rc>RC_CPLT_NOT_ALIGNED_ERR</rc> + <description>Chiplet not aligned</description> + <ffdc>TARGET_CHIPLET</ffdc> + <collectRegisterFfdc> + <id>NET_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CPLT_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CPLT_CONFIG_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>OTHER_CPLT_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>OPCG_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CC_STATUS_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>ERROR_STATUS_OF_CC</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CC_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <ffdc>PERV_CPLT_STAT0</ffdc> + <ffdc>LOOP_COUNT</ffdc> + <ffdc>HW_DELAY</ffdc> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <sbeError/> + <rc>RC_CPLT_OPCG_DONE_NOT_SET_ERR</rc> + <description>Chiplet OPCG_DONE not set after clock start/stop command</description> + <ffdc>TARGET_CHIPLET</ffdc> + <collectRegisterFfdc> + <id>NET_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CPLT_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CPLT_CONFIG_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>OTHER_CPLT_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>OPCG_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CC_STATUS_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>ERROR_STATUS_OF_CC</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CC_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <ffdc>PERV_CPLT_STAT0</ffdc> + <ffdc>LOOP_COUNT</ffdc> + <ffdc>HW_DELAY</ffdc> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <sbeError/> + <rc>RC_NEST_ARY_ERR</rc> + <description>ary_thold status not matching the expected value in clock start stop sequence</description> + <ffdc>TARGET_CHIPLET</ffdc> + <collectRegisterFfdc> + <id>NET_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CPLT_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CPLT_CONFIG_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>OTHER_CPLT_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>OPCG_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CC_STATUS_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>ERROR_STATUS_OF_CC</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CC_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <ffdc>READ_CLK_ARY</ffdc> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <sbeError/> + <rc>RC_NEST_NSL_ERR</rc> + <description>nsl_thold status not matching the expected value in clock start stop sequence</description> + <ffdc>TARGET_CHIPLET</ffdc> + <collectRegisterFfdc> + <id>NET_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CPLT_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CPLT_CONFIG_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>OTHER_CPLT_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>OPCG_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CC_STATUS_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>ERROR_STATUS_OF_CC</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CC_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <ffdc>READ_CLK_NSL</ffdc> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <sbeError/> + <rc>RC_NEST_SL_ERR</rc> + <description>sl_thold status not matching the expected value in clock start stop sequence</description> + <ffdc>TARGET_CHIPLET</ffdc> + <collectRegisterFfdc> + <id>NET_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CPLT_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CPLT_CONFIG_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>OTHER_CPLT_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>OPCG_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CC_STATUS_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>ERROR_STATUS_OF_CC</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CC_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <ffdc>READ_CLK_SL</ffdc> + </hwpError> + <!-- ******************************************************************** --> </hwpErrors> diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_npll_setup_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_npll_setup_errors.xml index 6a35384f..7f4cd186 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_npll_setup_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_npll_setup_errors.xml @@ -27,33 +27,77 @@ <!-- Halt codes for p9_sbe_npll_setup --> <hwpErrors> - <!-- ******************************************************************** --> - <hwpError> - <sbeError/> - <rc>RC_SS_PLL_LOCK_ERR</rc> - <description>Spectrum pll not locked</description> - <ffdc>SS_PLL_READ</ffdc> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <sbeError/> - <rc>RC_CP_FILTER_PLL_LOCK_ERR</rc> - <description>CP Filter PLL not locked</description> - <ffdc>CP_FILTER_PLL_READ</ffdc> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <sbeError/> - <rc>RC_NEST_PLL_ERR</rc> - <description>Nest PLL not locked</description> - <ffdc>NEST_PLL_READ</ffdc> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <sbeError/> - <rc>RC_IO_FILTER_PLL_LOCK_ERR</rc> - <description>IO Filter PLL not locked</description> - <ffdc>IO_FILTER_PLL_READ</ffdc> - </hwpError> - <!-- ******************************************************************** --> + <sbeTarget>MASTER_CHIP</sbeTarget> + <!-- ******************************************************************** --> + <hwpError> + <sbeError/> + <rc>RC_SS_PLL_LOCK_ERR</rc> + <description>Spectrum pll not locked</description> + <collectRegisterFfdc> + <id>ROOT_CTRL_REGISTERS</id> + <target>MASTER_CHIP</target> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>PERV_CTRL_REGISTERS</id> + <target>MASTER_CHIP</target> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + </collectRegisterFfdc> + <ffdc>SS_PLL_READ</ffdc> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <sbeError/> + <rc>RC_CP_FILTER_PLL_LOCK_ERR</rc> + <description>CP Filter PLL not locked</description> + <collectRegisterFfdc> + <id>ROOT_CTRL_REGISTERS</id> + <target>MASTER_CHIP</target> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>PERV_CTRL_REGISTERS</id> + <target>MASTER_CHIP</target> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + </collectRegisterFfdc> + <ffdc>CP_FILTER_PLL_READ</ffdc> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <sbeError/> + <rc>RC_NEST_PLL_ERR</rc> + <description>Nest PLL not locked</description> + <collectRegisterFfdc> + <id>ROOT_CTRL_REGISTERS</id> + <target>MASTER_CHIP</target> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>PERV_CTRL_REGISTERS</id> + <target>MASTER_CHIP</target> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + </collectRegisterFfdc> + <ffdc>NEST_PLL_READ</ffdc> + <ffdc>SS_FILTER_BYPASS_STATUS</ffdc> + <ffdc>CP_FILTER_BYPASS_STATUS</ffdc> + <ffdc>IO_FILTER_BYPASS_STATUS</ffdc> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <sbeError/> + <rc>RC_IO_FILTER_PLL_LOCK_ERR</rc> + <description>IO Filter PLL not locked</description> + <collectRegisterFfdc> + <id>ROOT_CTRL_REGISTERS</id> + <target>MASTER_CHIP</target> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>PERV_CTRL_REGISTERS</id> + <target>MASTER_CHIP</target> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + </collectRegisterFfdc> + <ffdc>IO_FILTER_PLL_READ</ffdc> + </hwpError> + <!-- ******************************************************************** --> </hwpErrors> diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_tp_chiplet_init3_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_tp_chiplet_init3_errors.xml index ecb9eea0..86b68f2b 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_tp_chiplet_init3_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_tp_chiplet_init3_errors.xml @@ -25,19 +25,33 @@ <!-- This is an automatically generated file. --> <!-- File: p9_sbe_tp_chiplet_init3_errors.xml. --> <!-- Halt codes for p9_sbe_tp_chiplet_init3 --> - <hwpErrors> - <!-- ******************************************************************** --> - <hwpError> - <sbeError/> - <rc>RC_CALIBRATION_NOT_DONE</rc> - <description>Precision Reference Voltage : Calibration not done</description> - </hwpError> + <sbeTarget>MASTER_CHIP</sbeTarget> <!-- ******************************************************************** --> <hwpError> <sbeError/> <rc>RC_MF_OSC_ERR</rc> <description>MF Oscillator error active</description> + <collectRegisterFfdc> + <id>ROOT_CTRL_REGISTERS</id> + <target>MASTER_CHIP</target> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>PERV_CTRL_REGISTERS</id> + <target>MASTER_CHIP</target> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>OSC_ERROR_HOLD</id> + <target>MASTER_CHIP</target> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>OSC_SWITCH_SENSE_REGISTER</id> + <target>MASTER_CHIP</target> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + </collectRegisterFfdc> <ffdc>READ_OSCERR_HOLD</ffdc> </hwpError> <!-- ******************************************************************** --> @@ -45,6 +59,26 @@ <sbeError/> <rc>RC_MF_OSC_NOT_TOGGLE</rc> <description>MF Oscillator not toggling</description> + <collectRegisterFfdc> + <id>ROOT_CTRL_REGISTERS</id> + <target>MASTER_CHIP</target> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>PERV_CTRL_REGISTERS</id> + <target>MASTER_CHIP</target> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>OSC_ERROR_HOLD</id> + <target>MASTER_CHIP</target> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>OSC_SWITCH_SENSE_REGISTER</id> + <target>MASTER_CHIP</target> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + </collectRegisterFfdc> <ffdc>READ_SNS1LTH</ffdc> </hwpError> <!-- ******************************************************************** --> diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_tp_switch_gears_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_tp_switch_gears_errors.xml index f70d2788..dc19c862 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_tp_switch_gears_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_tp_switch_gears_errors.xml @@ -27,17 +27,55 @@ <!-- Halt codes for p9_sbe_tp_switch_gears --> <hwpErrors> + <sbeTarget>MASTER_CHIP</sbeTarget> <!-- ******************************************************************** --> - <hwpError> - <sbeError/> - <rc>RC_BUS_STATUS_BUSY0</rc> - <description>Status busy check</description> + <hwpError> + <sbeError/> + <rc>RC_I2C_BUS_STATUS_BUSY</rc> + <description>I2C seeprom port is not responding</description> + <collectRegisterFfdc> + <id>ROOT_CTRL_REGISTERS</id> + <target>MASTER_CHIP</target> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>PERV_CTRL_REGISTERS</id> + <target>MASTER_CHIP</target> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>I2C_REGISTERS</id> + <target>MASTER_CHIP</target> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + </collectRegisterFfdc> + <ffdc>STATUS_REGISTER_B</ffdc> + <ffdc>LOOP_COUNT</ffdc> </hwpError> <!-- ******************************************************************** --> <hwpError> - <sbeError/> - <rc>RC_MAGIC_NUMBER_NOT_VALID</rc> - <description>Magic number not matching</description> - </hwpError> + <sbeError/> + <rc>RC_MAGIC_NUMBER_NOT_VALID</rc> + <description>Magic number not matching from Seeprom + read with Fused number in OTPROM + </description> + <collectRegisterFfdc> + <id>ROOT_CTRL_REGISTERS</id> + <target>MASTER_CHIP</target> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>PERV_CTRL_REGISTERS</id> + <target>MASTER_CHIP</target> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>I2C_REGISTERS</id> + <target>MASTER_CHIP</target> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + </collectRegisterFfdc> + <ffdc>DATA0TO7_REGISTER_B</ffdc> + <ffdc>MAGIC_NUMBER_VALUE</ffdc> + <ffdc>BACKUP_SEEPROM_ATTR</ffdc> + </hwpError> <!-- ******************************************************************** --> </hwpErrors> |