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| author | Joachim Fenkes <fenkes@de.ibm.com> | 2017-04-07 11:03:28 +0200 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2017-06-02 00:43:47 -0400 |
| commit | 0a6c00308918a09b33cdeb39b273c655c382e707 (patch) | |
| tree | e426e6824a1c954e6825a1c5d4f6f7bca20ff396 | |
| parent | b3ef5463c77961a4925d93903680a241ba754e5b (diff) | |
| download | talos-sbe-0a6c00308918a09b33cdeb39b273c655c382e707.tar.gz talos-sbe-0a6c00308918a09b33cdeb39b273c655c382e707.zip | |
p9_fastarray: Add support for multiple chips, Nimbus DD2 support
Refactor engine code to switch from a fixed array and ring table to
a table per chip and EC level. Change a lot of loop constructs to
C++11-y foreach loops in the process.
Add a function to choose the right tables based on chip type and EC.
Also add Nimbus DD2 array and ring definitions.
Change-Id: I9d9ffeacc8bfe7f43a7afc7b73d5b831fb8db354
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40078
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: James N. Klazynski <jklazyns@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40130
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
| -rw-r--r-- | src/import/chips/p9/procedures/xml/error_info/p9_fastarray.xml | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_fastarray.xml b/src/import/chips/p9/procedures/xml/error_info/p9_fastarray.xml index 85e1b2cd..845de987 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_fastarray.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_fastarray.xml @@ -39,6 +39,12 @@ <ffdc>TARGET_TYPE</ffdc> </hwpError> <hwpError> + <rc>RC_FASTARRAY_UNKNOWN_RING</rc> + <description>An array specified a ring ID that was not defined in the ring table</description> + <ffdc>ARRAY_ID</ffdc> + <ffdc>RING_ID</ffdc> + </hwpError> + <hwpError> <rc>RC_RS5_RANGE_OUT_OF_ORDER</rc> <description>A range was added to an RS5 care list that violated the "in order of increasing start bit" requirement.</description> </hwpError> @@ -65,6 +71,12 @@ <rc>RC_FASTARRAY_CLOCK_TIMEOUT</rc> <description>An attempt to clock ABIST cycles did not complete within 100ms</description> </hwpError> + <hwpError> + <rc>RC_FASTARRAY_UNKNOWN_CHIP_EC</rc> + <description>There is no fastarray control data available for the requested chip type / EC</description> + <ffdc>CHIP_NAME</ffdc> + <ffdc>CHIP_EC</ffdc> + </hwpError> <!-- template for copying <hwpError> <rc>RC_FASTARRAY_</rc> |
