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| author | Doug Gilbert <dgilbert@us.ibm.com> | 2017-08-23 15:09:27 -0500 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2017-09-14 11:56:23 -0400 |
| commit | f978e9c225936f9b1a206323179c95d69116c0a3 (patch) | |
| tree | 16c95334dda354843dbd48de3f6a62cd655ece0d | |
| parent | d7db485f501c56f7c52402cbd9808a68e86c640f (diff) | |
| download | talos-sbe-f978e9c225936f9b1a206323179c95d69116c0a3.tar.gz talos-sbe-f978e9c225936f9b1a206323179c95d69116c0a3.zip | |
PK,IOTA: Enter idle state at a known location
Change-Id: I83498782420ff51891b692021330c643d0ffe74c
RTC: 178914
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45068
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Adam S. Hale <adam.samuel.hale@ibm.com>
Reviewed-by: Juan R. Medina <jrmedina@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45075
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
| -rw-r--r-- | src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_exceptions.S | 19 | ||||
| -rw-r--r-- | src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_msr.h | 4 |
2 files changed, 22 insertions, 1 deletions
diff --git a/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_exceptions.S b/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_exceptions.S index 9545b819..5efb2073 100644 --- a/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_exceptions.S +++ b/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_exceptions.S @@ -61,6 +61,20 @@ __machine_check: PPE42_MACHINE_CHECK_HANDLER ############################################################ + # 0x0020 : set MSR function + ############################################################ + + # If the MSR_WE bit is set, the PPE engine enters WAIT mode (idle) + # and this function provides a known address for the idle state. + + ############################################################ + .global __set_msr + .org __vectors + 0x0028 +__set_msr: + mtmsr %r3 + blr + + ############################################################ # 0x0040 : System Reset ############################################################ .global __system_reset @@ -185,7 +199,10 @@ __pk_idle_thread_from_bootloader: _lwzsd %r3, __pk_thread_machine_context_default _oriwa %r3, %r3, MSR_WE - mtmsr %r3 + bl __set_msr + + # The following jump-to-self is for SIMICS, which does not + # support or detect MSR_WE b . ## pk_halt() is implemented on the ppe42 by writing a value of 0x3 to diff --git a/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_msr.h b/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_msr.h index 1806ee2e..ae1cb405 100644 --- a/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_msr.h +++ b/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_msr.h @@ -112,6 +112,10 @@ #define wrtee(other_msr) \ asm volatile ("wrtee %0" : : "r" (other_msr) : "memory") +extern void __set_msr(unsigned int i_msr_value); + +#define ppe_idle() __set_msr(mfmsr() | MSR_WE | MSR_EE); + #endif /* __ASSEMBLER__ */ #endif /* __PPE42_MSR_H__ */ |
