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| author | Brian Silver <bsilver@us.ibm.com> | 2016-08-17 08:29:44 -0500 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2018-12-17 20:34:01 -0600 |
| commit | a7bf0135fb18c462f5bdca06ee614c956891b1db (patch) | |
| tree | 974efcaeae7a765a5d988f1fba0544770c1312a1 | |
| parent | b7da4b95261b32c3d2943d43297a41826afe7a65 (diff) | |
| download | talos-sbe-a7bf0135fb18c462f5bdca06ee614c956891b1db.tar.gz talos-sbe-a7bf0135fb18c462f5bdca06ee614c956891b1db.zip | |
Implement MRW attributes; dram_clks, db_util, 2n_mode
ATTR_MSS_MRW_MEM_M_DRAM_CLOCKS
ATTR_MSS_MRW_MAX_DRAM_DATABUS_UTIL
ATTR_MSS_MRW_DRAM_2N_MODE
TSYS_ADR, TSYS_DATA moved the MT VPD
GPO, RLO, WLO moved to the MT VPD
Update hb defaults
Update unit test to catch the 2N mode MRW changes
Change-Id: I3d998c70d30df978062ce923096ba741d597782e
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28383
Dev-Ready: Brian R. Silver <bsilver@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/69778
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Tested-by: Sachin Gupta <sgupta2m@in.ibm.com>
| -rw-r--r-- | src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml | 15 |
1 files changed, 0 insertions, 15 deletions
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml index 74414642..56b05254 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml @@ -2121,21 +2121,6 @@ </attribute> <attribute> - <id>ATTR_MSS_DATABUS_UTIL</id> - <targetType>TARGET_TYPE_MCS</targetType> - <!-- TK Do we need an attr per port & dimm ? P8 only had an attr per port AAM --> - <!-- TK Does OCC set this for their use, if so, name attr appropriately? AAM --> - <description> - DRAM data bus utilization percent to use to determine cfg_nm_n_per_port - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <writeable/> - <array>2</array> - <mssAccessorName>databus_util</mssAccessorName> - </attribute> - - <attribute> <id>ATTR_MSS_OCC_THROTTLED_N_CMDS</id> <targetType>TARGET_TYPE_MCS</targetType> <!-- TK Do we need an attr per port & dimm ? P8 only had an attr per port AAM --> |
