talos-sbe/src, branch 07-25-2019

Disable SBE console print as it significantly slows down SBE execution Status information is already transmitted over Port 81h/82h to the host system

2020-02-19T20:45:33+00:00

Send IPL status codes to BMC over LPC port 81h/82h

2020-02-19T20:45:33+00:00

Signed-off-by: Timothy Pearson

Add SPD, ATTR, and code support for thermal sensor fields

2020-02-18T17:06:14+00:00

In order to not break systems with old DDIMMs or old Explorer FW, this commit includes a workaround to bypass the thermal field parsing if the SPD revision is less than 0.3, as the decoder will try to parse garbage. This can be replaced down the line if needed with a proper API. git-coreq:hostboot:I7400886b90b566bbfdf218bcedf11627acf1d2fd Change-Id: I7400886b90b566bbfdf218bcedf11627acf1d2fd Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/87999 Tested-by: FSP CI Jenkins Dev-Ready: Mark Pizzutillo Tested-by: PPE CI Tested-by: HWSV CI Reviewed-by: Louis Stermole Tested-by: Jenkins Server Reviewed-by: STEPHEN GLANCY Tested-by: Hostboot CI Reviewed-by: Jennifer A Stofer Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/88583 Reviewed-by: RAJA DAS

Refactor PMIC attributes to be at OCMB level

2020-02-17T14:49:35+00:00

eff_config can now put SPD attributes at OCMB level if the attribute is defined as such. It will ignore any values for DIMM 1 and only use those for DIMM 0 (attributes that will be the same, like PMIC fields, for example) Minor fix to pmic_status_tool_ut failing UTs due to mismatch in help screen git-coreq:hostboot:I5a66f0540ecc65434123c976d83103c99d9ae018 Change-Id: I5a66f0540ecc65434123c976d83103c99d9ae018 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/90584 Tested-by: FSP CI Jenkins Tested-by: Jenkins Server Tested-by: PPE CI Tested-by: Hostboot CI Tested-by: HWSV CI Reviewed-by: Louis Stermole Reviewed-by: ANDRE A MARIN Reviewed-by: Jennifer A Stofer Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/90830 Reviewed-by: RAJA DAS

Adjust idec algorithm for Explorer B.0 format

2020-02-07T16:52:33+00:00

The update to B.0 doesn't allow for a change to the register that previously contained the MAJOR_REVISION value. Because of that we are revising the logic that determines the EC level to be a lookup based on a single number instead. Ignore the MAJOR_RELEASE field from CHIP_INFO entirely, it will always =1. Instead we will rely only on the EFUSE bits currently designated for MINOR_RELEASE. Since we lost the ability to have a common M.m we will just use a single incrementing value to represent the ordinal revision number, regardless of major/minor, i.e. the 1st revision is 0, the 2nd is 1, the 10th is 9, etc. So that gives us these values for EFUSE_IMAGE_OUT_3[13:10] A.0 = 0 = 0x10 in Host Firmware A.1 = 1 = 0x11 in Host Firmware B.0 = 2 = 0x20 in Host Firmware B.1 = 3 = 0x21 in Host Firmware (if it were to happen) Change-Id: I878491e8e004c231ce4dcd7abe887a947c7f3dc3 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/89764 Tested-by: FSP CI Jenkins Tested-by: Jenkins Server Tested-by: PPE CI Reviewed-by: Louis Stermole Tested-by: Hostboot CI Reviewed-by: Christian R Geddes Reviewed-by: Jennifer A Stofer Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/89793 Reviewed-by: RAJA DAS

Add attribute for SPD_REVISION (byte 1)

2020-02-07T16:51:56+00:00

Rename previous uses of Byte 192, the ddimm module spd section to avoid ambiguity. Renamed from spd_revision --> ddimm_module_spd_revision git-coreq:hostboot:I039173097619111ae5847660472e75ed9f2d5f1d git-coreq:sbe:I039173097619111ae5847660472e75ed9f2d5f1d git-coreq:hwsv:I039173097619111ae5847660472e75ed9f2d5f1d Change-Id: I039173097619111ae5847660472e75ed9f2d5f1d Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/90410 Tested-by: FSP CI Jenkins Tested-by: Jenkins Server Tested-by: HWSV CI Tested-by: PPE CI Reviewed-by: STEPHEN GLANCY Tested-by: Hostboot CI Reviewed-by: Louis Stermole Reviewed-by: Jennifer A Stofer Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/90506 Reviewed-by: RAJA DAS

Add TARGET_TYPE_GENERICI2CSLAVE and relevant attributes

2020-02-07T16:51:20+00:00

Change-Id: I7d7579f66aba39ab8a462215417e7ab7745f3a6b Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/90321 Tested-by: FSP CI Jenkins Tested-by: Jenkins Server Tested-by: HWSV CI Tested-by: PPE CI Tested-by: Hostboot CI Reviewed-by: STEPHEN GLANCY Reviewed-by: Louis Stermole Reviewed-by: Jennifer A Stofer Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/90331 Reviewed-by: RAJA DAS

Update EnterMPIPL to collect architected dumps and

2020-02-07T14:22:48+00:00

stopClocks for BMC based system Change-Id: Iac0b82e12f048e593acb54c82815d890c2ae93a6 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/90183 Tested-by: Jenkins Server Tested-by: FSP CI Jenkins Reviewed-by: RAJA DAS

Use full UART TX buffer (shave 5s off booting)

2020-02-04T13:58:39+00:00

This patch makes us use the full TX buffer of the UART rather than waiting for each character to go through. This practically means we get a *massive* IPL speed up. Measured on my Raptor Blackbird with P9N DD2.21, from "Welcome to SBE" to "Booting Hostboot" (timed on a stopwatch): Before (with UART output): 15 seconds With this patch (with UART output): 10 seconds. A full 33% reduction in boot time for SBE is nothing to sneeze at! Change-Id: Iac50d4b820f3b998e55e5f6e0bff60b067c1df45 Signed-off-by: Stewart Smith Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/90587 Tested-by: Jenkins Server Reviewed-by: Andrew R Jeffery Tested-by: FSP CI Jenkins Reviewed-by: RAJA DAS

Update the Simics release path

2020-02-03T11:24:57+00:00

Change-Id: I046e248d8815080f97a5f259315e8a6f7a9e9da5 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/90657 Tested-by: Jenkins Server Tested-by: FSP CI Jenkins Reviewed-by: RAJA DAS