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<title>talos-sbe/src/test/framework, branch 07-25-2019</title>
<subtitle>Blackbird™ SBE sources</subtitle>
<id>https://git.raptorcs.com/git/talos-sbe/atom?h=07-25-2019</id>
<link rel='self' href='https://git.raptorcs.com/git/talos-sbe/atom?h=07-25-2019'/>
<link rel='alternate' type='text/html' href='https://git.raptorcs.com/git/talos-sbe/'/>
<updated>2019-05-30T10:41:21+00:00</updated>
<entry>
<title>AXONE Bringup CI</title>
<updated>2019-05-30T10:41:21+00:00</updated>
<author>
<name>Sunil Kumar</name>
<email>skumar8j@in.ibm.com</email>
</author>
<published>2018-11-15T06:20:34+00:00</published>
<link rel='alternate' type='text/html' href='https://git.raptorcs.com/git/talos-sbe/commit/?id=01030a212c0793d0f8c84c8ff187fe7db0e07df7'/>
<id>urn:sha1:01030a212c0793d0f8c84c8ff187fe7db0e07df7</id>
<content type='text'>
Change-Id: I611879498fe0b728547209716cecf6d940a9a820
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/72837
Tested-by: Jenkins Server &lt;pfd-jenkins+hostboot@us.ibm.com&gt;
Tested-by: FSP CI Jenkins &lt;fsp-CI-jenkins+hostboot@us.ibm.com&gt;
Reviewed-by: RAJA DAS &lt;rajadas2@in.ibm.com&gt;
</content>
</entry>
<entry>
<title>Update Backing build to customrc and update standalone simics patch</title>
<updated>2019-04-10T08:27:45+00:00</updated>
<author>
<name>Raja Das</name>
<email>rajadas2@in.ibm.com</email>
</author>
<published>2019-02-06T03:21:33+00:00</published>
<link rel='alternate' type='text/html' href='https://git.raptorcs.com/git/talos-sbe/commit/?id=4bd48045fe9aa99f55d328a860dbc39ca8fa2815'/>
<id>urn:sha1:4bd48045fe9aa99f55d328a860dbc39ca8fa2815</id>
<content type='text'>
Change-Id: I8ca9aef300a3ef5808db84e28ea80d1dd524e794
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71415
Tested-by: Jenkins Server &lt;pfd-jenkins+hostboot@us.ibm.com&gt;
Tested-by: FSP CI Jenkins &lt;fsp-CI-jenkins+hostboot@us.ibm.com&gt;
Reviewed-by: MURULIDHAR NATARAJU &lt;murulidhar@in.ibm.com&gt;
Reviewed-by: RAJA DAS &lt;rajadas2@in.ibm.com&gt;
</content>
</entry>
<entry>
<title>Jenkins parallel build</title>
<updated>2018-09-17T07:30:38+00:00</updated>
<author>
<name>spashabk-in</name>
<email>shakeebbk@in.ibm.com</email>
</author>
<published>2018-09-17T06:13:04+00:00</published>
<link rel='alternate' type='text/html' href='https://git.raptorcs.com/git/talos-sbe/commit/?id=da99f39710df224314573b411f0fd5ca8743c743'/>
<id>urn:sha1:da99f39710df224314573b411f0fd5ca8743c743</id>
<content type='text'>
Make fix
enable parallel build in jenkins

Change-Id: If75ecb600f632492c2a7fa68999249d5321a7166
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/66204
Tested-by: Jenkins Server &lt;pfd-jenkins+hostboot@us.ibm.com&gt;
Reviewed-by: Sachin Gupta &lt;sgupta2m@in.ibm.com&gt;
</content>
</entry>
<entry>
<title>[SBE-ARCH1]HRMOR relocated to 4Gb for SPLess Opal system</title>
<updated>2018-08-30T05:29:53+00:00</updated>
<author>
<name>Raja Das</name>
<email>rajadas2@in.ibm.com</email>
</author>
<published>2018-03-22T04:29:02+00:00</published>
<link rel='alternate' type='text/html' href='https://git.raptorcs.com/git/talos-sbe/commit/?id=bd5c4de63cdd033e0c6b2ec55e4ff65c17b8dc43'/>
<id>urn:sha1:bd5c4de63cdd033e0c6b2ec55e4ff65c17b8dc43</id>
<content type='text'>
-removed s0s1 compile time flag

-64MBytes * 64 = 4096MBytes Address

-Updated simics patch to hack the Fspbit to be set, so that for SBE
 Jenkins testing, SBE picks up the default 128MB HRMOR.

Change-Id: I77eb5cb018b1f684b4322f23c2b64307bfe1e230
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/56151
Tested-by: Jenkins Server &lt;pfd-jenkins+hostboot@us.ibm.com&gt;
Tested-by: FSP CI Jenkins &lt;fsp-CI-jenkins+hostboot@us.ibm.com&gt;
Reviewed-by: Shakeeb A. Pasha B K &lt;shakeebbk@in.ibm.com&gt;
Reviewed-by: Sachin Gupta &lt;sgupta2m@in.ibm.com&gt;
</content>
</entry>
<entry>
<title>Update backing build</title>
<updated>2018-03-27T07:15:04+00:00</updated>
<author>
<name>Sachin Gupta</name>
<email>sgupta2m@in.ibm.com</email>
</author>
<published>2018-03-27T05:25:33+00:00</published>
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<id>urn:sha1:e5725003060d185aa62fc244f724e09624a228ea</id>
<content type='text'>
Change-Id: Iee198aeaeec6003bcec40b93fb47647ad15bf91f
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56284
Tested-by: Jenkins Server &lt;pfd-jenkins+hostboot@us.ibm.com&gt;
Reviewed-by: Sachin Gupta &lt;sgupta2m@in.ibm.com&gt;
</content>
</entry>
<entry>
<title>p9_sbe_lpc_init: Fix timeout setup</title>
<updated>2018-03-19T08:32:15+00:00</updated>
<author>
<name>Joachim Fenkes</name>
<email>fenkes@de.ibm.com</email>
</author>
<published>2018-02-21T08:24:02+00:00</published>
<link rel='alternate' type='text/html' href='https://git.raptorcs.com/git/talos-sbe/commit/?id=da13fade1742d95eb1d4d8edc9cb03e9270e4947'/>
<id>urn:sha1:da13fade1742d95eb1d4d8edc9cb03e9270e4947</id>
<content type='text'>
Factor LPC register access out into its own utility function, with
added timeout for the ADU access and proper FFDC if the ADU times out.

CQ: SW418354
cmvc-prereq: 1048349
Change-Id: Ief05ccb022eeb1ec45d2f49f386fb58231966058
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54637
Tested-by: FSP CI Jenkins &lt;fsp-CI-jenkins+hostboot@us.ibm.com&gt;
Reviewed-by: Joseph J. McGill &lt;jmcgill@us.ibm.com&gt;
Tested-by: Jenkins Server &lt;pfd-jenkins+hostboot@us.ibm.com&gt;
Tested-by: HWSV CI &lt;hwsv-ci+hostboot@us.ibm.com&gt;
Tested-by: Hostboot CI &lt;hostboot-ci+hostboot@us.ibm.com&gt;
Tested-by: PPE CI &lt;ppe-ci+hostboot@us.ibm.com&gt;
Reviewed-by: Prachi Gupta &lt;pragupta@us.ibm.com&gt;
Reviewed-by: Jennifer A. Stofer &lt;stofer@us.ibm.com&gt;
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54641
Reviewed-by: Sachin Gupta &lt;sgupta2m@in.ibm.com&gt;
</content>
</entry>
<entry>
<title>[SBE-code-re-org][6] Build configuration</title>
<updated>2018-01-19T09:26:41+00:00</updated>
<author>
<name>spashabk-in</name>
<email>shakeebbk@in.ibm.com</email>
</author>
<published>2017-12-09T15:36:11+00:00</published>
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<id>urn:sha1:8a863e816e41837dc954eba4b0962efcb0117889</id>
<content type='text'>
Makefile re-org for project specific build

Change-Id: I51893710979f19cf00e41725c83d1c0c653c4b60
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50744
Tested-by: Jenkins Server &lt;pfd-jenkins+hostboot@us.ibm.com&gt;
Tested-by: FSP CI Jenkins &lt;fsp-CI-jenkins+hostboot@us.ibm.com&gt;
Reviewed-by: Sachin Gupta &lt;sgupta2m@in.ibm.com&gt;
</content>
</entry>
<entry>
<title>PM: Fix QCSR and CCSR update</title>
<updated>2017-11-13T17:04:20+00:00</updated>
<author>
<name>Prasad Bg Ranganath</name>
<email>prasadbgr@in.ibm.com</email>
</author>
<published>2017-10-18T13:56:54+00:00</published>
<link rel='alternate' type='text/html' href='https://git.raptorcs.com/git/talos-sbe/commit/?id=5556610f48c24f02c4f3f505274c70f64207de4c'/>
<id>urn:sha1:5556610f48c24f02c4f3f505274c70f64207de4c</id>
<content type='text'>
- Use base addresses vs set addresses to ensure that all fields are correct

cmvc-prereq:1037315
CQ:SW405722
Change-Id: I330c309131ac4ac44c6dc294627e1ff02d33004a
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48552
Tested-by: Jenkins Server &lt;pfd-jenkins+hostboot@us.ibm.com&gt;
Tested-by: PPE CI &lt;ppe-ci+hostboot@us.ibm.com&gt;
Tested-by: Hostboot CI &lt;hostboot-ci+hostboot@us.ibm.com&gt;
Reviewed-by: Gregory S. Still &lt;stillgs@us.ibm.com&gt;
Reviewed-by: Juan R. Medina &lt;jrmedina@us.ibm.com&gt;
Reviewed-by: Jennifer A. Stofer &lt;stofer@us.ibm.com&gt;
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48557
Tested-by: FSP CI Jenkins &lt;fsp-CI-jenkins+hostboot@us.ibm.com&gt;
Reviewed-by: Sachin Gupta &lt;sgupta2m@in.ibm.com&gt;
</content>
</entry>
<entry>
<title>TOR Magic header support</title>
<updated>2017-10-04T06:10:26+00:00</updated>
<author>
<name>Claus Michael Olsen</name>
<email>cmolsen@us.ibm.com</email>
</author>
<published>2017-01-25T05:42:50+00:00</published>
<link rel='alternate' type='text/html' href='https://git.raptorcs.com/git/talos-sbe/commit/?id=d5ee3e8dd56be6c8e7030d8fbc77827e1c292027'/>
<id>urn:sha1:d5ee3e8dd56be6c8e7030d8fbc77827e1c292027</id>
<content type='text'>
HW-Image-Coreq=Yes
SBE-Image-Coreq=No (SBE image is back compatible)

This commit adds an 12-byte header to all TOR ring sections:
- for improved self-containment of TOR ring sections incl
  stand-alone ring sections like .overrides which, currently,
  has no meaningful size info associated with it in the PNOR,
- to support a more data-driven implementation of TOR API,
- to eliminate the current usage of XIP_MAGIC ids to inform the
  TOR APIs which ring section they are dealing with, and
- to improve debugging binary ring sections.

The TOR header expands on the current TorNumDdLevels field in the
HW ring section and is added to all other ring sections as well,
e.g. for the SBE and OVRD ring sections.  Most importantly, the
TOR header adds the TOR magic number which is unique for each
possible TOR ring section. Also, of quite practical importance,
a size field has been added so that the size of a true standalone
section like .overrides can be extracted (since its size in PNOR
is not indicative of its size).

Further, to support the use of ddLevel and chipType in the TOR
header fields, these two data points need to be always supplied
whenever calling ring_apply. Thus, updates have been made to the
ring_apply.mk file as well as the override .pl script.  While
making these changes, we also decided to change the --type arg
to the --bOverrides arg to make the arguments being passed less
confusing in view of the Centaur commit that's coming and its
demands to make codes less data dependent, incl make and script
files which should simply inform the functional intent of the
"user". The user shouldn't presume it knows about which specific
type of ring section needs to be produced.

Further, the DD level block struct has been increased from 8B
to 12B to avoid the unnecessarily complex merging of the
ddLevel and offset into the same 4B field. It's included in
this commit since this is also going to break the lab and
because the required code changes are in the same places
where the code changes needed for the TOR header are.

Further, xip_tool has been updated to support the new TOR
header so that it can be called by supplying a standalone
ring section, such as overrides.bin. Various changes have
been made in xip_tool's dissect section to support overrides
as well.

This code uses many  of the code changes in 33778 except
changes to p9_tor.C|H are at a bare minimum focusing on the
functional changes and keeping any cleanups to a minimum changing
only some variable names associated with the functional changes
for improved readability of the code.

CMVC-Prereq: 1034144
CMVC-Prereq: 1035575
Change-Id: I29ba8905ac55dad5c10878a94fb94468e5580ea0
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35372
Tested-by: Jenkins Server &lt;pfd-jenkins+hostboot@us.ibm.com&gt;
Tested-by: HWSV CI &lt;hwsv-ci+hostboot@us.ibm.com&gt;
Reviewed-by: Jennifer A. Stofer &lt;stofer@us.ibm.com&gt;
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37993
Reviewed-by: Hostboot Team &lt;hostboot@us.ibm.com&gt;
Tested-by: FSP CI Jenkins &lt;fsp-CI-jenkins+hostboot@us.ibm.com&gt;
Reviewed-by: Sachin Gupta &lt;sgupta2m@in.ibm.com&gt;
</content>
</entry>
<entry>
<title>SBE FW security switch</title>
<updated>2017-09-06T11:54:36+00:00</updated>
<author>
<name>spashabk-in</name>
<email>shakeebbk@in.ibm.com</email>
</author>
<published>2017-08-22T11:35:07+00:00</published>
<link rel='alternate' type='text/html' href='https://git.raptorcs.com/git/talos-sbe/commit/?id=75a82b734c4c5aaa274ed8e90401b00fa0e5df95'/>
<id>urn:sha1:75a82b734c4c5aaa274ed8e90401b00fa0e5df95</id>
<content type='text'>
Implement SBE firmware security switch
based on ATTR_SECURITY_ENABLE

Change-Id: I435aad38c59e80c81925bd1f4b109aafd1993b1c
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44959
Tested-by: Jenkins Server &lt;pfd-jenkins+hostboot@us.ibm.com&gt;
Reviewed-by: Sachin Gupta &lt;sgupta2m@in.ibm.com&gt;
</content>
</entry>
</feed>
