talos-sbe/src/test/framework/etc, branch master

[SBE-ARCH1]HRMOR relocated to 4Gb for SPLess Opal system

2018-08-30T05:29:53+00:00

-removed s0s1 compile time flag -64MBytes * 64 = 4096MBytes Address -Updated simics patch to hack the Fspbit to be set, so that for SBE Jenkins testing, SBE picks up the default 128MB HRMOR. Change-Id: I77eb5cb018b1f684b4322f23c2b64307bfe1e230 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/56151 Tested-by: Jenkins Server Tested-by: FSP CI Jenkins Reviewed-by: Shakeeb A. Pasha B K Reviewed-by: Sachin Gupta

Update backing build

2018-03-27T07:15:04+00:00

Change-Id: Iee198aeaeec6003bcec40b93fb47647ad15bf91f Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56284 Tested-by: Jenkins Server Reviewed-by: Sachin Gupta

p9_sbe_lpc_init: Fix timeout setup

2018-03-19T08:32:15+00:00

Factor LPC register access out into its own utility function, with added timeout for the ADU access and proper FFDC if the ADU times out. CQ: SW418354 cmvc-prereq: 1048349 Change-Id: Ief05ccb022eeb1ec45d2f49f386fb58231966058 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54637 Tested-by: FSP CI Jenkins Reviewed-by: Joseph J. McGill Tested-by: Jenkins Server Tested-by: HWSV CI Tested-by: Hostboot CI Tested-by: PPE CI Reviewed-by: Prachi Gupta Reviewed-by: Jennifer A. Stofer Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54641 Reviewed-by: Sachin Gupta

PM: Fix QCSR and CCSR update

2017-11-13T17:04:20+00:00

- Use base addresses vs set addresses to ensure that all fields are correct cmvc-prereq:1037315 CQ:SW405722 Change-Id: I330c309131ac4ac44c6dc294627e1ff02d33004a Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48552 Tested-by: Jenkins Server Tested-by: PPE CI Tested-by: Hostboot CI Reviewed-by: Gregory S. Still Reviewed-by: Juan R. Medina Reviewed-by: Jennifer A. Stofer Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48557 Tested-by: FSP CI Jenkins Reviewed-by: Sachin Gupta

TOR Magic header support

2017-10-04T06:10:26+00:00

HW-Image-Coreq=Yes SBE-Image-Coreq=No (SBE image is back compatible) This commit adds an 12-byte header to all TOR ring sections: - for improved self-containment of TOR ring sections incl stand-alone ring sections like .overrides which, currently, has no meaningful size info associated with it in the PNOR, - to support a more data-driven implementation of TOR API, - to eliminate the current usage of XIP_MAGIC ids to inform the TOR APIs which ring section they are dealing with, and - to improve debugging binary ring sections. The TOR header expands on the current TorNumDdLevels field in the HW ring section and is added to all other ring sections as well, e.g. for the SBE and OVRD ring sections. Most importantly, the TOR header adds the TOR magic number which is unique for each possible TOR ring section. Also, of quite practical importance, a size field has been added so that the size of a true standalone section like .overrides can be extracted (since its size in PNOR is not indicative of its size). Further, to support the use of ddLevel and chipType in the TOR header fields, these two data points need to be always supplied whenever calling ring_apply. Thus, updates have been made to the ring_apply.mk file as well as the override .pl script. While making these changes, we also decided to change the --type arg to the --bOverrides arg to make the arguments being passed less confusing in view of the Centaur commit that's coming and its demands to make codes less data dependent, incl make and script files which should simply inform the functional intent of the "user". The user shouldn't presume it knows about which specific type of ring section needs to be produced. Further, the DD level block struct has been increased from 8B to 12B to avoid the unnecessarily complex merging of the ddLevel and offset into the same 4B field. It's included in this commit since this is also going to break the lab and because the required code changes are in the same places where the code changes needed for the TOR header are. Further, xip_tool has been updated to support the new TOR header so that it can be called by supplying a standalone ring section, such as overrides.bin. Various changes have been made in xip_tool's dissect section to support overrides as well. This code uses many of the code changes in 33778 except changes to p9_tor.C|H are at a bare minimum focusing on the functional changes and keeping any cleanups to a minimum changing only some variable names associated with the functional changes for improved readability of the code. CMVC-Prereq: 1034144 CMVC-Prereq: 1035575 Change-Id: I29ba8905ac55dad5c10878a94fb94468e5580ea0 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35372 Tested-by: Jenkins Server Tested-by: HWSV CI Reviewed-by: Jennifer A. Stofer Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37993 Reviewed-by: Hostboot Team Tested-by: FSP CI Jenkins Reviewed-by: Sachin Gupta

SBE FW security switch

2017-09-06T11:54:36+00:00

Implement SBE firmware security switch based on ATTR_SECURITY_ENABLE Change-Id: I435aad38c59e80c81925bd1f4b109aafd1993b1c Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44959 Tested-by: Jenkins Server Reviewed-by: Sachin Gupta

Solve CI issue

2017-03-29T06:16:36+00:00

Change-Id: I054e2f173cc1b4c5361f2c9c0908c337b4cf4c1e Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38566 Tested-by: Jenkins Server Tested-by: FSP CI Jenkins Reviewed-by: Sachin Gupta

Core Init additions to put ABIST engines in parallel mode for Nimbus DD1.0

2017-03-21T08:34:44+00:00

CMVC-Prereq:1019352 RTC:167284 Change-Id: I167c63950f72eb0446e3dd746ebd1e12adfb9f69 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36962 Tested-by: Jenkins Server Tested-by: PPE CI Reviewed-by: ASHISH A. MORE Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA Reviewed-by: Prem Shanker Jha Tested-by: Hostboot CI Reviewed-by: Benjamin Gass Reviewed-by: Joseph J. McGill Reviewed-by: Jennifer A. Stofer Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36965 Reviewed-by: Hostboot Team Tested-by: FSP CI Jenkins Reviewed-by: Sachin Gupta

Update backing build

2017-02-03T04:42:12+00:00

Change-Id: Iae5cdb6050c4b6623e5795e32fbb2852da2c874f Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35870 Tested-by: Jenkins Server Reviewed-by: Sachin Gupta

TOR space reductions

2017-01-25T14:15:07+00:00

These changes avoid some waste of valuable memory used to store TOR and rings contained in TOR. This is mostly needed as a SEEPROM relief. Contains: - 12 byte ring header (former 31551 commit) - less zero padding at the end of compressed ring (former 31524 commit) - removed an additional ring meta data structure (former 31524 commit) In addition, it contains these fixes: - fixed a bunch of scan addresses (former 33969 commit) - increased size of ring decompression buffer (former 32796 commit) - zero byte ring padding up to 4 byte boundaries for SBE (former 33969 commit) - added dbgl control of error trace after call to get_ring_from_sbe_image - added enumerated ringId to the RS4v3 header - fixed incorrect scan address masks for even/odd EX RS4 v3 ring handling in MVPD accessor functions - fixed incorrect scan address region bits for odd EX rings translated from RS4 v2 to RS4 v3 in MVPD accessor functions CMVC-Prereq: 1015124 Change-Id: I8fd00760e6ac2b3760994d1ca819fffbf35188ca Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33993 Tested-by: Hostboot CI Tested-by: Jenkins Server Tested-by: PPE CI Reviewed-by: Prachi Gupta Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34014 Reviewed-by: Sachin Gupta