talos-sbe/src/sbefw, branch 07-25-2019

Send IPL status codes to BMC over LPC port 81h/82h

2020-02-19T20:45:33+00:00

Signed-off-by: Timothy Pearson

Update EnterMPIPL to collect architected dumps and

2020-02-07T14:22:48+00:00

stopClocks for BMC based system Change-Id: Iac0b82e12f048e593acb54c82815d890c2ae93a6 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/90183 Tested-by: Jenkins Server Tested-by: FSP CI Jenkins Reviewed-by: RAJA DAS

Use full UART TX buffer (shave 5s off booting)

2020-02-04T13:58:39+00:00

This patch makes us use the full TX buffer of the UART rather than waiting for each character to go through. This practically means we get a *massive* IPL speed up. Measured on my Raptor Blackbird with P9N DD2.21, from "Welcome to SBE" to "Booting Hostboot" (timed on a stopwatch): Before (with UART output): 15 seconds With this patch (with UART output): 10 seconds. A full 33% reduction in boot time for SBE is nothing to sneeze at! Change-Id: Iac50d4b820f3b998e55e5f6e0bff60b067c1df45 Signed-off-by: Stewart Smith Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/90587 Tested-by: Jenkins Server Reviewed-by: Andrew R Jeffery Tested-by: FSP CI Jenkins Reviewed-by: RAJA DAS

Setting the HRMOR value for OPAL based systems.

2020-01-10T10:23:44+00:00

Change-Id: I75f01f8996c6664641bca939855a7bcad6220a01 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/87387 Tested-by: Jenkins Server Reviewed-by: MURULIDHAR NATARAJU Tested-by: FSP CI Jenkins Reviewed-by: RAJA DAS

Run LPC Init to clean up errors on MPIPL

2019-11-11T04:13:30+00:00

Recently HBBL added some error checking on LPC accesses Unfortunately OPAL leaves some errors in the accumulated status register of the LPC Host Controller. Since HBBL doesn't have the space to clear... have the SBE run lpc_init on MPIPL to clean up Keep a global alias for HRMOR Attribute in Pibmem Fetch the SPMode from Default SPMODE Attr if Mbox8 valid bit is not set, else fetch it from Mbox3 bit3. This is to support BMC scratch register setting which are all NULL Change-Id: I975311d9313ac8dbe70cf4595a96c43faaa98dd7 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/86434 Tested-by: Jenkins Server Tested-by: FSP CI Jenkins Reviewed-by: RAJA DAS

Optimized the Control Instruction Chip-op

2019-09-30T11:36:03+00:00

- Simics doesn't handle core2 onwards properly for control Instruction. It fails with invalid clock state for core2 onwards. CecChip::isValidClocksState Invalid clocks state [0x00000000 0x00000001] to SCOM 0x22010a9c (clockBits [0xe0000000 0x00000001]) - Need to comeback on this to see why simics doesn't complain about core0/1. Change-Id: Id6480b041e4e1ddb29e448ce1653e0995887db2e Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/82990 Tested-by: Jenkins Server Tested-by: FSP CI Jenkins Reviewed-by: RAJA DAS

Removed FlushNVDIMM from MPIPL Path

2019-07-09T12:31:22+00:00

Hwsv is already handling flushNVDIMM call before calling enterMPIPL There it also checks if flushNVDIMM needs to be skipped basis ARM'ed status of the NVDIMM. With this change, SBE is only supporting the chip-op call now. Change-Id: I44c4bb93c624556c615e9c623c28b282a5ec4de7 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/80131 Tested-by: Jenkins Server Tested-by: FSP CI Jenkins Reviewed-by: Dean Sanner Reviewed-by: RAJA DAS

Support Collect DUMP in ZZ-L system

2019-06-27T04:10:10+00:00

Update the sbeCollectDumpMpipl() to return response data in the case of success Change-Id: Ifeafb05b3e3ba39eaf868b88bb926e7836ad5203 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/73533 Tested-by: Jenkins Server Reviewed-by: MURULIDHAR NATARAJU Tested-by: FSP CI Jenkins Reviewed-by: RAJA DAS

AXONE Bringup CI

2019-05-30T10:41:21+00:00

Change-Id: I611879498fe0b728547209716cecf6d940a9a820 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/72837 Tested-by: Jenkins Server Tested-by: FSP CI Jenkins Reviewed-by: RAJA DAS

White/Black/Grey List Binary dump full SBE implementation

2019-03-14T09:07:39+00:00

Change-Id: I7e547677102edb93b562dae767fd5a01b86958ce Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/70842 Tested-by: Jenkins Server Tested-by: FSP CI Jenkins Reviewed-by: RAJA DAS