<feed xmlns='http://www.w3.org/2005/Atom'>
<title>talos-sbe/src/hwpf, branch 07-25-2019</title>
<subtitle>Blackbird™ SBE sources</subtitle>
<id>https://git.raptorcs.com/git/talos-sbe/atom?h=07-25-2019</id>
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<updated>2020-01-10T10:23:44+00:00</updated>
<entry>
<title>Setting the HRMOR value for OPAL based systems.</title>
<updated>2020-01-10T10:23:44+00:00</updated>
<author>
<name>vinaybs6</name>
<email>vinaybs6@in.ibm.com</email>
</author>
<published>2019-11-19T12:41:38+00:00</published>
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<id>urn:sha1:54f3205f2ce678cf8d377f4d3d5c23b3bce33096</id>
<content type='text'>
Change-Id: I75f01f8996c6664641bca939855a7bcad6220a01
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/87387
Tested-by: Jenkins Server &lt;pfd-jenkins+hostboot@us.ibm.com&gt;
Reviewed-by: MURULIDHAR NATARAJU &lt;murulidhar@in.ibm.com&gt;
Tested-by: FSP CI Jenkins &lt;fsp-CI-jenkins+hostboot@us.ibm.com&gt;
Reviewed-by: RAJA DAS &lt;rajadas2@in.ibm.com&gt;
</content>
</entry>
<entry>
<title>Run LPC Init to clean up errors on MPIPL</title>
<updated>2019-11-11T04:13:30+00:00</updated>
<author>
<name>Dean Sanner</name>
<email>dsanner@us.ibm.com</email>
</author>
<published>2019-11-04T01:58:29+00:00</published>
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<id>urn:sha1:c05bb41d728e6fc05a34d9d02320d6e37a6a79a4</id>
<content type='text'>
Recently HBBL added some error checking on LPC accesses
Unfortunately OPAL leaves some errors in the accumulated
status register of the LPC Host Controller.

Since HBBL doesn't have the space to clear... have the
SBE run lpc_init on MPIPL to clean up

Keep a global alias for HRMOR Attribute in Pibmem

Fetch the SPMode from Default SPMODE Attr if Mbox8 valid bit is
not set, else fetch it from Mbox3 bit3.
This is to support BMC scratch register setting which are all NULL

Change-Id: I975311d9313ac8dbe70cf4595a96c43faaa98dd7
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/86434
Tested-by: Jenkins Server &lt;pfd-jenkins+hostboot@us.ibm.com&gt;
Tested-by: FSP CI Jenkins &lt;fsp-CI-jenkins+hostboot@us.ibm.com&gt;
Reviewed-by: RAJA DAS &lt;rajadas2@in.ibm.com&gt;
</content>
</entry>
<entry>
<title>Updated HRMOR to 3968MB (64MB * 62) less than</title>
<updated>2019-04-04T15:26:26+00:00</updated>
<author>
<name>Murulidhar Nataraju</name>
<email>murulidhar@in.ibm.com</email>
</author>
<published>2019-04-04T06:59:58+00:00</published>
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<id>urn:sha1:249671d79a098be1068df41754a258483aa17614</id>
<content type='text'>
4GB so as to fit it in 32 bits (mbox scratch reg)
for OPAL based systems

Change-Id: I85441c47e80fa3af0f8e576ae59400079b808250
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/75512
Tested-by: Jenkins Server &lt;pfd-jenkins+hostboot@us.ibm.com&gt;
Tested-by: FSP CI Jenkins &lt;fsp-CI-jenkins+hostboot@us.ibm.com&gt;
Reviewed-by: RAJA DAS &lt;rajadas2@in.ibm.com&gt;
</content>
</entry>
<entry>
<title>FAPI2: Multicast API 1/2: Platform-breaking changes</title>
<updated>2019-02-14T03:37:51+00:00</updated>
<author>
<name>Joachim Fenkes</name>
<email>fenkes@de.ibm.com</email>
</author>
<published>2018-12-05T15:47:55+00:00</published>
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<id>urn:sha1:b9b668e5916e3310eacb95496cc0792d819b25f0</id>
<content type='text'>
The Target gains a new template parameter, M, that specifies
the multicast type. This is propagated through all affected
header files.

A new target type is introduced, TARGET_TYPE_MULTICAST, and
platform specific assertions put in place to prevent users
from creating such targets before the platform supports it.

Target also grows a new inline function for updating MC targets.
Platforms not supporting MC can provide a dummy implementation.

The example platform code in fapi2/include/plat/plat_target.H
is updated with minimal example code for platform implementers.

Change-Id: Ia0990f26890dc5c719caca608cd134a4964a3acf
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/69456
Tested-by: Jenkins Server &lt;pfd-jenkins+hostboot@us.ibm.com&gt;
Tested-by: HWSV CI &lt;hwsv-ci+hostboot@us.ibm.com&gt;
Tested-by: FSP CI Jenkins &lt;fsp-CI-jenkins+hostboot@us.ibm.com&gt;
Reviewed-by: Matt K. Light &lt;mklight@us.ibm.com&gt;
Tested-by: PPE CI &lt;ppe-ci+hostboot@us.ibm.com&gt;
Tested-by: Hostboot CI &lt;hostboot-ci+hostboot@us.ibm.com&gt;
Reviewed-by: Daniel M. Crowell &lt;dcrowell@us.ibm.com&gt;
Reviewed-by: RAJA DAS &lt;rajadas2@in.ibm.com&gt;
Reviewed-by: Jennifer A. Stofer &lt;stofer@us.ibm.com&gt;
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/70866
Reviewed-by: Sachin Gupta &lt;sgupta2m@in.ibm.com&gt;
</content>
</entry>
<entry>
<title>Mark OB1 and OB2 present for Axone</title>
<updated>2019-01-11T05:40:37+00:00</updated>
<author>
<name>Santosh Puranik</name>
<email>santosh.puranik@in.ibm.com</email>
</author>
<published>2018-12-07T08:40:31+00:00</published>
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<id>urn:sha1:8fd3e3a6f64c351149a1a8f0486c0dd82fae4977</id>
<content type='text'>
Change-Id: Idf3b3d8099d06987e60d4e22bb5be45114761ee4
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/69550
Tested-by: Jenkins Server &lt;pfd-jenkins+hostboot@us.ibm.com&gt;
Tested-by: FSP CI Jenkins &lt;fsp-CI-jenkins+hostboot@us.ibm.com&gt;
Reviewed-by: Sachin Gupta &lt;sgupta2m@in.ibm.com&gt;
</content>
</entry>
<entry>
<title>Axone chipId support</title>
<updated>2018-10-24T11:35:41+00:00</updated>
<author>
<name>Raja Das</name>
<email>rajadas2@in.ibm.com</email>
</author>
<published>2018-10-24T05:39:04+00:00</published>
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<id>urn:sha1:2992583ae8c95e4418fd4791ef279e65ccf2159b</id>
<content type='text'>
Change-Id: I19c59782b617b03872b2fd2330a0c6f1f76ec866
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/67928
Tested-by: Jenkins Server &lt;pfd-jenkins+hostboot@us.ibm.com&gt;
Tested-by: FSP CI Jenkins &lt;fsp-CI-jenkins+hostboot@us.ibm.com&gt;
Reviewed-by: Sachin Gupta &lt;sgupta2m@in.ibm.com&gt;
</content>
</entry>
<entry>
<title>Simics check in case of spless system before modifying HRMOR to 4GB</title>
<updated>2018-09-21T10:57:59+00:00</updated>
<author>
<name>Raja Das</name>
<email>rajadas2@in.ibm.com</email>
</author>
<published>2018-09-21T09:46:35+00:00</published>
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<id>urn:sha1:26acfd0fd5e7df0053336bd8ee1baba9e1e926dc</id>
<content type='text'>
Change-Id: Ife2ae7699350a8570ed212cfaaf1feff4a6c894b
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/66457
Tested-by: Jenkins Server &lt;pfd-jenkins+hostboot@us.ibm.com&gt;
Reviewed-by: Sachin Gupta &lt;sgupta2m@in.ibm.com&gt;
</content>
</entry>
<entry>
<title>[SBE-ARCH1]HRMOR relocated to 4Gb for SPLess Opal system</title>
<updated>2018-08-30T05:29:53+00:00</updated>
<author>
<name>Raja Das</name>
<email>rajadas2@in.ibm.com</email>
</author>
<published>2018-03-22T04:29:02+00:00</published>
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<id>urn:sha1:bd5c4de63cdd033e0c6b2ec55e4ff65c17b8dc43</id>
<content type='text'>
-removed s0s1 compile time flag

-64MBytes * 64 = 4096MBytes Address

-Updated simics patch to hack the Fspbit to be set, so that for SBE
 Jenkins testing, SBE picks up the default 128MB HRMOR.

Change-Id: I77eb5cb018b1f684b4322f23c2b64307bfe1e230
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/56151
Tested-by: Jenkins Server &lt;pfd-jenkins+hostboot@us.ibm.com&gt;
Tested-by: FSP CI Jenkins &lt;fsp-CI-jenkins+hostboot@us.ibm.com&gt;
Reviewed-by: Shakeeb A. Pasha B K &lt;shakeebbk@in.ibm.com&gt;
Reviewed-by: Sachin Gupta &lt;sgupta2m@in.ibm.com&gt;
</content>
</entry>
<entry>
<title>Add hook to setup ATTR_SMF_CONFIG</title>
<updated>2018-08-29T04:44:50+00:00</updated>
<author>
<name>Dean Sanner</name>
<email>dsanner@us.ibm.com</email>
</author>
<published>2018-08-14T14:55:56+00:00</published>
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<id>urn:sha1:69dedc0ffc2656e357a8115ffd76bbec39f1cf07</id>
<content type='text'>
  Read from scratch register and set SBE ATTR

Change-Id: I5c9b7022fda7803ece8d438efafc5ae3787aafcc
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64412
Tested-by: Jenkins Server &lt;pfd-jenkins+hostboot@us.ibm.com&gt;
Tested-by: FSP CI Jenkins &lt;fsp-CI-jenkins+hostboot@us.ibm.com&gt;
Reviewed-by: Sachin Gupta &lt;sgupta2m@in.ibm.com&gt;
</content>
</entry>
<entry>
<title>Risk level 3/4/5 support: Step 2 - image update to TOR v7</title>
<updated>2018-05-03T15:31:38+00:00</updated>
<author>
<name>Claus Michael Olsen</name>
<email>cmolsen@us.ibm.com</email>
</author>
<published>2018-04-18T14:08:07+00:00</published>
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<id>urn:sha1:34332987f42c5e806dc15d87de9bb79305a5c95b</id>
<content type='text'>
- This commit updates the image ring sections to TOR v7.
- It will fail with EKB FSP CI until we include the prereq to the
  merged step 1 commit in PPE and HB.

Key_Cronus_Test=XIP_REGRESS

cmvc-prereq: 1053262
cmvc-prereq: 1053182
Change-Id: Ie7452fe42877297da4f0da5cd4e51c989b6ac28d
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57421
Tested-by: Jenkins Server &lt;pfd-jenkins+hostboot@us.ibm.com&gt;
Tested-by: HWSV CI &lt;hwsv-ci+hostboot@us.ibm.com&gt;
Tested-by: PPE CI &lt;ppe-ci+hostboot@us.ibm.com&gt;
Tested-by: Hostboot CI &lt;hostboot-ci+hostboot@us.ibm.com&gt;
Tested-by: Cronus HW CI &lt;cronushw-ci+hostboot@us.ibm.com&gt;
Tested-by: FSP CI Jenkins &lt;fsp-CI-jenkins+hostboot@us.ibm.com&gt;
Reviewed-by: James N. Klazynski &lt;jklazyns@us.ibm.com&gt;
Reviewed-by: Joseph J. McGill &lt;jmcgill@us.ibm.com&gt;
Reviewed-by: Jennifer A. Stofer &lt;stofer@us.ibm.com&gt;
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57432
Reviewed-by: Sachin Gupta &lt;sgupta2m@in.ibm.com&gt;
</content>
</entry>
</feed>
