/* * Copyright 2015 - Maxime Coquelin * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual * licensing only applies to this file, and not this project as a * whole. * * a) This file is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of the * License, or (at your option) any later version. * * This file is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation * files (the "Software"), to deal in the Software without * restriction, including without limitation the rights to use, * copy, modify, merge, publish, distribute, sublicense, and/or * sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following * conditions: * * The above copyright notice and this permission notice shall be * included in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ #include "skeleton.dtsi" #include "armv7-m.dtsi" #include #include #include / { clocks { clk_hse: clk-hse { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <0>; }; clk-lse { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; }; clk-lsi { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32000>; }; clk_i2s_ckin: clk-i2s-ckin { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <48000000>; }; }; soc { timer2: timer@40000000 { compatible = "st,stm32-timer"; reg = <0x40000000 0x400>; interrupts = <28>; clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>; status = "disabled"; }; timer3: timer@40000400 { compatible = "st,stm32-timer"; reg = <0x40000400 0x400>; interrupts = <29>; clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>; status = "disabled"; }; timer4: timer@40000800 { compatible = "st,stm32-timer"; reg = <0x40000800 0x400>; interrupts = <30>; clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>; status = "disabled"; }; timer5: timer@40000c00 { compatible = "st,stm32-timer"; reg = <0x40000c00 0x400>; interrupts = <50>; clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>; }; timer6: timer@40001000 { compatible = "st,stm32-timer"; reg = <0x40001000 0x400>; interrupts = <54>; clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>; status = "disabled"; }; timer7: timer@40001400 { compatible = "st,stm32-timer"; reg = <0x40001400 0x400>; interrupts = <55>; clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>; status = "disabled"; }; rtc: rtc@40002800 { compatible = "st,stm32-rtc"; reg = <0x40002800 0x400>; clocks = <&rcc 1 CLK_RTC>; clock-names = "ck_rtc"; assigned-clocks = <&rcc 1 CLK_RTC>; assigned-clock-parents = <&rcc 1 CLK_LSE>; interrupt-parent = <&exti>; interrupts = <17 1>; interrupt-names = "alarm"; st,syscfg = <&pwrcfg>; status = "disabled"; }; usart2: serial@40004400 { compatible = "st,stm32f7-usart", "st,stm32f7-uart"; reg = <0x40004400 0x400>; interrupts = <38>; clocks = <&rcc 1 CLK_USART2>; status = "disabled"; }; usart3: serial@40004800 { compatible = "st,stm32f7-usart", "st,stm32f7-uart"; reg = <0x40004800 0x400>; interrupts = <39>; clocks = <&rcc 1 CLK_USART3>; status = "disabled"; }; usart4: serial@40004c00 { compatible = "st,stm32f7-uart"; reg = <0x40004c00 0x400>; interrupts = <52>; clocks = <&rcc 1 CLK_UART4>; status = "disabled"; }; usart5: serial@40005000 { compatible = "st,stm32f7-uart"; reg = <0x40005000 0x400>; interrupts = <53>; clocks = <&rcc 1 CLK_UART5>; status = "disabled"; }; usart7: serial@40007800 { compatible = "st,stm32f7-usart", "st,stm32f7-uart"; reg = <0x40007800 0x400>; interrupts = <82>; clocks = <&rcc 1 CLK_UART7>; status = "disabled"; }; usart8: serial@40007c00 { compatible = "st,stm32f7-usart", "st,stm32f7-uart"; reg = <0x40007c00 0x400>; interrupts = <83>; clocks = <&rcc 1 CLK_UART8>; status = "disabled"; }; usart1: serial@40011000 { compatible = "st,stm32f7-usart", "st,stm32f7-uart"; reg = <0x40011000 0x400>; interrupts = <37>; clocks = <&rcc 1 CLK_USART1>; status = "disabled"; }; usart6: serial@40011400 { compatible = "st,stm32f7-usart", "st,stm32f7-uart"; reg = <0x40011400 0x400>; interrupts = <71>; clocks = <&rcc 1 CLK_USART6>; status = "disabled"; }; syscfg: system-config@40013800 { compatible = "syscon"; reg = <0x40013800 0x400>; }; exti: interrupt-controller@40013c00 { compatible = "st,stm32-exti"; interrupt-controller; #interrupt-cells = <2>; reg = <0x40013C00 0x400>; interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>; }; pwrcfg: power-config@40007000 { compatible = "syscon"; reg = <0x40007000 0x400>; }; pin-controller { #address-cells = <1>; #size-cells = <1>; compatible = "st,stm32f746-pinctrl"; ranges = <0 0x40020000 0x3000>; interrupt-parent = <&exti>; st,syscfg = <&syscfg 0x8>; pins-are-numbered; gpioa: gpio@40020000 { gpio-controller; #gpio-cells = <2>; reg = <0x0 0x400>; clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>; st,bank-name = "GPIOA"; }; gpiob: gpio@40020400 { gpio-controller; #gpio-cells = <2>; reg = <0x400 0x400>; clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>; st,bank-name = "GPIOB"; }; gpioc: gpio@40020800 { gpio-controller; #gpio-cells = <2>; reg = <0x800 0x400>; clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>; st,bank-name = "GPIOC"; }; gpiod: gpio@40020c00 { gpio-controller; #gpio-cells = <2>; reg = <0xc00 0x400>; clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>; st,bank-name = "GPIOD"; }; gpioe: gpio@40021000 { gpio-controller; #gpio-cells = <2>; reg = <0x1000 0x400>; clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>; st,bank-name = "GPIOE"; }; gpiof: gpio@40021400 { gpio-controller; #gpio-cells = <2>; reg = <0x1400 0x400>; clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>; st,bank-name = "GPIOF"; }; gpiog: gpio@40021800 { gpio-controller; #gpio-cells = <2>; reg = <0x1800 0x400>; clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>; st,bank-name = "GPIOG"; }; gpioh: gpio@40021c00 { gpio-controller; #gpio-cells = <2>; reg = <0x1c00 0x400>; clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>; st,bank-name = "GPIOH"; }; gpioi: gpio@40022000 { gpio-controller; #gpio-cells = <2>; reg = <0x2000 0x400>; clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>; st,bank-name = "GPIOI"; }; gpioj: gpio@40022400 { gpio-controller; #gpio-cells = <2>; reg = <0x2400 0x400>; clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>; st,bank-name = "GPIOJ"; }; gpiok: gpio@40022800 { gpio-controller; #gpio-cells = <2>; reg = <0x2800 0x400>; clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>; st,bank-name = "GPIOK"; }; usart1_pins_a: usart1@0 { pins1 { pinmux = ; bias-disable; drive-push-pull; slew-rate = <0>; }; pins2 { pinmux = ; bias-disable; }; }; }; rcc: rcc@40023800 { #clock-cells = <2>; compatible = "st,stm32f746-rcc", "st,stm32-rcc"; reg = <0x40023800 0x400>; clocks = <&clk_hse>, <&clk_i2s_ckin>; st,syscfg = <&pwrcfg>; assigned-clocks = <&rcc 1 CLK_HSE_RTC>; assigned-clock-rates = <1000000>; }; }; }; &systick { clocks = <&rcc 1 0>; status = "okay"; };