From 9899b81e7ca5c285b825ff10ca9357dd18813d83 Mon Sep 17 00:00:00 2001 From: Mike Sinkovsky Date: Wed, 4 Apr 2012 19:33:53 +0000 Subject: Ethernet driver for the WIZnet W5300 chip Based on original driver from chip manufacturer, but nearly full rewite. Tested and used in production with Blackfin BF531 embedded processor. Signed-off-by: Mike Sinkovsky Signed-off-by: David S. Miller --- include/linux/platform_data/wiznet.h | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 include/linux/platform_data/wiznet.h (limited to 'include/linux/platform_data') diff --git a/include/linux/platform_data/wiznet.h b/include/linux/platform_data/wiznet.h new file mode 100644 index 000000000000..b5d8c192d84d --- /dev/null +++ b/include/linux/platform_data/wiznet.h @@ -0,0 +1,24 @@ +/* + * Ethernet driver for the WIZnet W5x00 chip. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef PLATFORM_DATA_WIZNET_H +#define PLATFORM_DATA_WIZNET_H + +#include + +struct wiznet_platform_data { + int link_gpio; + u8 mac_addr[ETH_ALEN]; +}; + +#ifndef CONFIG_WIZNET_BUS_SHIFT +#define CONFIG_WIZNET_BUS_SHIFT 0 +#endif + +#define W5100_BUS_DIRECT_SIZE (0x8000 << CONFIG_WIZNET_BUS_SHIFT) +#define W5300_BUS_DIRECT_SIZE (0x0400 << CONFIG_WIZNET_BUS_SHIFT) + +#endif /* PLATFORM_DATA_WIZNET_H */ -- cgit v1.2.3 From 434103adea3f63f6550f4b2bd16653328f933a66 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 16 Mar 2012 16:06:07 -0600 Subject: usb: ehci-tegra: Add vbus_gpio to platform data Add a vbus_gpio field to platform data. This mirrors the device tree property nvidia,vbus-gpio. This makes the VBUS GPIO handling identical between booting with board files and device tree; the driver always does it. This removes the need for board files to request and initialize the GPIO early during their boot process, perhaps even before the GPIO driver is ready to process the request. Cc: Greg Kroah-Hartman Cc: Alan Stern Cc: linux-usb@vger.kernel.org Signed-off-by: Stephen Warren Acked-by: Olof Johansson --- arch/arm/mach-tegra/devices.c | 3 +++ drivers/usb/host/ehci-tegra.c | 13 +++++++------ include/linux/platform_data/tegra_usb.h | 1 + 3 files changed, 11 insertions(+), 6 deletions(-) (limited to 'include/linux/platform_data') diff --git a/arch/arm/mach-tegra/devices.c b/arch/arm/mach-tegra/devices.c index 5f6b867e20b4..748b40cb7fcf 100644 --- a/arch/arm/mach-tegra/devices.c +++ b/arch/arm/mach-tegra/devices.c @@ -448,17 +448,20 @@ static struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = { struct tegra_ehci_platform_data tegra_ehci1_pdata = { .operating_mode = TEGRA_USB_OTG, .power_down_on_bus_suspend = 1, + .vbus_gpio = -1, }; struct tegra_ehci_platform_data tegra_ehci2_pdata = { .phy_config = &tegra_ehci2_ulpi_phy_config, .operating_mode = TEGRA_USB_HOST, .power_down_on_bus_suspend = 1, + .vbus_gpio = -1, }; struct tegra_ehci_platform_data tegra_ehci3_pdata = { .operating_mode = TEGRA_USB_HOST, .power_down_on_bus_suspend = 1, + .vbus_gpio = -1, }; static u64 tegra_ehci_dmamask = DMA_BIT_MASK(32); diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c index 73544bd440bd..9692bef159f5 100644 --- a/drivers/usb/host/ehci-tegra.c +++ b/drivers/usb/host/ehci-tegra.c @@ -581,15 +581,16 @@ static const struct hc_driver tegra_ehci_hc_driver = { .port_handed_over = ehci_port_handed_over, }; -static int setup_vbus_gpio(struct platform_device *pdev) +static int setup_vbus_gpio(struct platform_device *pdev, + struct tegra_ehci_platform_data *pdata) { int err = 0; int gpio; - if (!pdev->dev.of_node) - return 0; - - gpio = of_get_named_gpio(pdev->dev.of_node, "nvidia,vbus-gpio", 0); + gpio = pdata->vbus_gpio; + if (!gpio_is_valid(gpio)) + gpio = of_get_named_gpio(pdev->dev.of_node, + "nvidia,vbus-gpio", 0); if (!gpio_is_valid(gpio)) return 0; @@ -633,7 +634,7 @@ static int tegra_ehci_probe(struct platform_device *pdev) if (!pdev->dev.dma_mask) pdev->dev.dma_mask = &tegra_ehci_dma_mask; - setup_vbus_gpio(pdev); + setup_vbus_gpio(pdev, pdata); tegra = kzalloc(sizeof(struct tegra_ehci_hcd), GFP_KERNEL); if (!tegra) diff --git a/include/linux/platform_data/tegra_usb.h b/include/linux/platform_data/tegra_usb.h index 6bca5b569acb..66c673fef408 100644 --- a/include/linux/platform_data/tegra_usb.h +++ b/include/linux/platform_data/tegra_usb.h @@ -26,6 +26,7 @@ struct tegra_ehci_platform_data { /* power down the phy on bus suspend */ int power_down_on_bus_suspend; void *phy_config; + int vbus_gpio; }; #endif /* _TEGRA_USB_H_ */ -- cgit v1.2.3 From 3e0c70d050c7ed6d163897a6ac894f063c31b10f Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Thu, 12 Apr 2012 15:48:49 +0900 Subject: usb: ehci-sh: Add PHY init function with platform data In devices using ehci-sh, initialization of the PHY may be necessary. This adds platform data to ehci-sh and provide function to initialize PHY. Signed-off-by: Nobuhiro Iwamatsu CC: Shimoda, Yoshihiro Acked-by: Paul Mundt Signed-off-by: Greg Kroah-Hartman --- drivers/usb/host/ehci-sh.c | 8 ++++++++ include/linux/platform_data/ehci-sh.h | 28 ++++++++++++++++++++++++++++ 2 files changed, 36 insertions(+) create mode 100644 include/linux/platform_data/ehci-sh.h (limited to 'include/linux/platform_data') diff --git a/drivers/usb/host/ehci-sh.c b/drivers/usb/host/ehci-sh.c index 9d9cf47d80da..ca819cdd0c5e 100644 --- a/drivers/usb/host/ehci-sh.c +++ b/drivers/usb/host/ehci-sh.c @@ -11,6 +11,7 @@ */ #include #include +#include struct ehci_sh_priv { struct clk *iclk, *fclk; @@ -100,6 +101,7 @@ static int ehci_hcd_sh_probe(struct platform_device *pdev) const struct hc_driver *driver = &ehci_sh_hc_driver; struct resource *res; struct ehci_sh_priv *priv; + struct ehci_sh_platdata *pdata; struct usb_hcd *hcd; int irq, ret; @@ -124,6 +126,9 @@ static int ehci_hcd_sh_probe(struct platform_device *pdev) goto fail_create_hcd; } + if (pdev->dev.platform_data != NULL) + pdata = pdev->dev.platform_data; + /* initialize hcd */ hcd = usb_create_hcd(&ehci_sh_hc_driver, &pdev->dev, dev_name(&pdev->dev)); @@ -168,6 +173,9 @@ static int ehci_hcd_sh_probe(struct platform_device *pdev) clk_enable(priv->fclk); clk_enable(priv->iclk); + if (pdata && pdata->phy_init) + pdata->phy_init(); + ret = usb_add_hcd(hcd, irq, IRQF_SHARED); if (ret != 0) { dev_err(&pdev->dev, "Failed to add hcd"); diff --git a/include/linux/platform_data/ehci-sh.h b/include/linux/platform_data/ehci-sh.h new file mode 100644 index 000000000000..5c15a738e116 --- /dev/null +++ b/include/linux/platform_data/ehci-sh.h @@ -0,0 +1,28 @@ +/* + * EHCI SuperH driver platform data + * + * Copyright (C) 2012 Nobuhiro Iwamatsu + * Copyright (C) 2012 Renesas Solutions Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __USB_EHCI_SH_H +#define __USB_EHCI_SH_H + +struct ehci_sh_platdata { + void (*phy_init)(void); /* Phy init function */ +}; + +#endif /* __USB_EHCI_SH_H */ -- cgit v1.2.3 From 7ec944538dde3d7f490bd4d2619051789db5c3c3 Mon Sep 17 00:00:00 2001 From: Aneesh V Date: Fri, 27 Apr 2012 17:54:05 +0530 Subject: memory: emif: add basic infrastructure for EMIF driver EMIF is an SDRAM controller used in various Texas Instruments SoCs. EMIF supports, based on its revision, one or more of LPDDR2/DDR2/DDR3 protocols. Add the basic infrastructure for EMIF driver that includes driver registration, probe, parsing of platform data etc. Signed-off-by: Aneesh V Reviewed-by: Santosh Shilimkar Reviewed-by: Benoit Cousson [santosh.shilimkar@ti.com: Moved to drivers/memory from drivers/misc] Signed-off-by: Santosh Shilimkar Tested-by: Lokesh Vutla Signed-off-by: Greg Kroah-Hartman --- Documentation/memory-devices/ti-emif.txt | 57 ++++++ drivers/Kconfig | 2 + drivers/Makefile | 1 + drivers/memory/Kconfig | 22 +++ drivers/memory/Makefile | 5 + drivers/memory/emif.c | 289 +++++++++++++++++++++++++++++++ drivers/memory/emif.h | 7 + include/linux/platform_data/emif_plat.h | 128 ++++++++++++++ 8 files changed, 511 insertions(+) create mode 100644 Documentation/memory-devices/ti-emif.txt create mode 100644 drivers/memory/Kconfig create mode 100644 drivers/memory/Makefile create mode 100644 drivers/memory/emif.c create mode 100644 include/linux/platform_data/emif_plat.h (limited to 'include/linux/platform_data') diff --git a/Documentation/memory-devices/ti-emif.txt b/Documentation/memory-devices/ti-emif.txt new file mode 100644 index 000000000000..f4ad9a7d0f4b --- /dev/null +++ b/Documentation/memory-devices/ti-emif.txt @@ -0,0 +1,57 @@ +TI EMIF SDRAM Controller Driver: + +Author +======== +Aneesh V + +Location +============ +driver/memory/emif.c + +Supported SoCs: +=================== +TI OMAP44xx +TI OMAP54xx + +Menuconfig option: +========================== +Device Drivers + Memory devices + Texas Instruments EMIF driver + +Description +=========== +This driver is for the EMIF module available in Texas Instruments +SoCs. EMIF is an SDRAM controller that, based on its revision, +supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols. +This driver takes care of only LPDDR2 memories presently. The +functions of the driver includes re-configuring AC timing +parameters and other settings during frequency, voltage and +temperature changes + +Platform Data (see include/linux/platform_data/emif_plat.h): +===================================================================== +DDR device details and other board dependent and SoC dependent +information can be passed through platform data (struct emif_platform_data) +- DDR device details: 'struct ddr_device_info' +- Device AC timings: 'struct lpddr2_timings' and 'struct lpddr2_min_tck' +- Custom configurations: customizable policy options through + 'struct emif_custom_configs' +- IP revision +- PHY type + +Interface to the external world: +================================ +EMIF driver registers notifiers for voltage and frequency changes +affecting EMIF and takes appropriate actions when these are invoked. +- freq_pre_notify_handling() +- freq_post_notify_handling() +- volt_notify_handling() + +Debugfs +======== +The driver creates two debugfs entries per device. +- regcache_dump : dump of register values calculated and saved for all + frequencies used so far. +- mr4 : last polled value of MR4 register in the LPDDR2 device. MR4 + indicates the current temperature level of the device. diff --git a/drivers/Kconfig b/drivers/Kconfig index 0233ad979b7d..63b81826cb55 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -142,4 +142,6 @@ source "drivers/devfreq/Kconfig" source "drivers/extcon/Kconfig" +source "drivers/memory/Kconfig" + endmenu diff --git a/drivers/Makefile b/drivers/Makefile index c41dfa92cd79..265b506a15be 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -135,3 +135,4 @@ obj-$(CONFIG_HYPERV) += hv/ obj-$(CONFIG_PM_DEVFREQ) += devfreq/ obj-$(CONFIG_EXTCON) += extcon/ +obj-$(CONFIG_MEMORY) += memory/ diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig new file mode 100644 index 000000000000..b08327cca0e5 --- /dev/null +++ b/drivers/memory/Kconfig @@ -0,0 +1,22 @@ +# +# Memory devices +# + +menuconfig MEMORY + bool "Memory Controller drivers" + +if MEMORY + +config TI_EMIF + tristate "Texas Instruments EMIF driver" + select DDR + help + This driver is for the EMIF module available in Texas Instruments + SoCs. EMIF is an SDRAM controller that, based on its revision, + supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols. + This driver takes care of only LPDDR2 memories presently. The + functions of the driver includes re-configuring AC timing + parameters and other settings during frequency, voltage and + temperature changes + +endif diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile new file mode 100644 index 000000000000..e27f80b28859 --- /dev/null +++ b/drivers/memory/Makefile @@ -0,0 +1,5 @@ +# +# Makefile for memory devices +# + +obj-$(CONFIG_TI_EMIF) += emif.o diff --git a/drivers/memory/emif.c b/drivers/memory/emif.c new file mode 100644 index 000000000000..7486d7ef0826 --- /dev/null +++ b/drivers/memory/emif.c @@ -0,0 +1,289 @@ +/* + * EMIF driver + * + * Copyright (C) 2012 Texas Instruments, Inc. + * + * Aneesh V + * Santosh Shilimkar + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "emif.h" + +/** + * struct emif_data - Per device static data for driver's use + * @duplicate: Whether the DDR devices attached to this EMIF + * instance are exactly same as that on EMIF1. In + * this case we can save some memory and processing + * @temperature_level: Maximum temperature of LPDDR2 devices attached + * to this EMIF - read from MR4 register. If there + * are two devices attached to this EMIF, this + * value is the maximum of the two temperature + * levels. + * @node: node in the device list + * @base: base address of memory-mapped IO registers. + * @dev: device pointer. + * @plat_data: Pointer to saved platform data. + */ +struct emif_data { + u8 duplicate; + u8 temperature_level; + struct list_head node; + void __iomem *base; + struct device *dev; + struct emif_platform_data *plat_data; +}; + +static struct emif_data *emif1; +static LIST_HEAD(device_list); + +static void get_default_timings(struct emif_data *emif) +{ + struct emif_platform_data *pd = emif->plat_data; + + pd->timings = lpddr2_jedec_timings; + pd->timings_arr_size = ARRAY_SIZE(lpddr2_jedec_timings); + + dev_warn(emif->dev, "%s: using default timings\n", __func__); +} + +static int is_dev_data_valid(u32 type, u32 density, u32 io_width, u32 phy_type, + u32 ip_rev, struct device *dev) +{ + int valid; + + valid = (type == DDR_TYPE_LPDDR2_S4 || + type == DDR_TYPE_LPDDR2_S2) + && (density >= DDR_DENSITY_64Mb + && density <= DDR_DENSITY_8Gb) + && (io_width >= DDR_IO_WIDTH_8 + && io_width <= DDR_IO_WIDTH_32); + + /* Combinations of EMIF and PHY revisions that we support today */ + switch (ip_rev) { + case EMIF_4D: + valid = valid && (phy_type == EMIF_PHY_TYPE_ATTILAPHY); + break; + case EMIF_4D5: + valid = valid && (phy_type == EMIF_PHY_TYPE_INTELLIPHY); + break; + default: + valid = 0; + } + + if (!valid) + dev_err(dev, "%s: invalid DDR details\n", __func__); + return valid; +} + +static int is_custom_config_valid(struct emif_custom_configs *cust_cfgs, + struct device *dev) +{ + int valid = 1; + + if ((cust_cfgs->mask & EMIF_CUSTOM_CONFIG_LPMODE) && + (cust_cfgs->lpmode != EMIF_LP_MODE_DISABLE)) + valid = cust_cfgs->lpmode_freq_threshold && + cust_cfgs->lpmode_timeout_performance && + cust_cfgs->lpmode_timeout_power; + + if (cust_cfgs->mask & EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL) + valid = valid && cust_cfgs->temp_alert_poll_interval_ms; + + if (!valid) + dev_warn(dev, "%s: invalid custom configs\n", __func__); + + return valid; +} + +static struct emif_data *__init_or_module get_device_details( + struct platform_device *pdev) +{ + u32 size; + struct emif_data *emif = NULL; + struct ddr_device_info *dev_info; + struct emif_custom_configs *cust_cfgs; + struct emif_platform_data *pd; + struct device *dev; + void *temp; + + pd = pdev->dev.platform_data; + dev = &pdev->dev; + + if (!(pd && pd->device_info && is_dev_data_valid(pd->device_info->type, + pd->device_info->density, pd->device_info->io_width, + pd->phy_type, pd->ip_rev, dev))) { + dev_err(dev, "%s: invalid device data\n", __func__); + goto error; + } + + emif = devm_kzalloc(dev, sizeof(*emif), GFP_KERNEL); + temp = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL); + dev_info = devm_kzalloc(dev, sizeof(*dev_info), GFP_KERNEL); + + if (!emif || !pd || !dev_info) { + dev_err(dev, "%s:%d: allocation error\n", __func__, __LINE__); + goto error; + } + + memcpy(temp, pd, sizeof(*pd)); + pd = temp; + memcpy(dev_info, pd->device_info, sizeof(*dev_info)); + + pd->device_info = dev_info; + emif->plat_data = pd; + emif->dev = dev; + emif->temperature_level = SDRAM_TEMP_NOMINAL; + + /* + * For EMIF instances other than EMIF1 see if the devices connected + * are exactly same as on EMIF1(which is typically the case). If so, + * mark it as a duplicate of EMIF1 and skip copying timings data. + * This will save some memory and some computation later. + */ + emif->duplicate = emif1 && (memcmp(dev_info, + emif1->plat_data->device_info, + sizeof(struct ddr_device_info)) == 0); + + if (emif->duplicate) { + pd->timings = NULL; + pd->min_tck = NULL; + goto out; + } else if (emif1) { + dev_warn(emif->dev, "%s: Non-symmetric DDR geometry\n", + __func__); + } + + /* + * Copy custom configs - ignore allocation error, if any, as + * custom_configs is not very critical + */ + cust_cfgs = pd->custom_configs; + if (cust_cfgs && is_custom_config_valid(cust_cfgs, dev)) { + temp = devm_kzalloc(dev, sizeof(*cust_cfgs), GFP_KERNEL); + if (temp) + memcpy(temp, cust_cfgs, sizeof(*cust_cfgs)); + else + dev_warn(dev, "%s:%d: allocation error\n", __func__, + __LINE__); + pd->custom_configs = temp; + } + + /* + * Copy timings and min-tck values from platform data. If it is not + * available or if memory allocation fails, use JEDEC defaults + */ + size = sizeof(struct lpddr2_timings) * pd->timings_arr_size; + if (pd->timings) { + temp = devm_kzalloc(dev, size, GFP_KERNEL); + if (temp) { + memcpy(temp, pd->timings, sizeof(*pd->timings)); + pd->timings = temp; + } else { + dev_warn(dev, "%s:%d: allocation error\n", __func__, + __LINE__); + get_default_timings(emif); + } + } else { + get_default_timings(emif); + } + + if (pd->min_tck) { + temp = devm_kzalloc(dev, sizeof(*pd->min_tck), GFP_KERNEL); + if (temp) { + memcpy(temp, pd->min_tck, sizeof(*pd->min_tck)); + pd->min_tck = temp; + } else { + dev_warn(dev, "%s:%d: allocation error\n", __func__, + __LINE__); + pd->min_tck = &lpddr2_jedec_min_tck; + } + } else { + pd->min_tck = &lpddr2_jedec_min_tck; + } + +out: + return emif; + +error: + return NULL; +} + +static int __init_or_module emif_probe(struct platform_device *pdev) +{ + struct emif_data *emif; + struct resource *res; + + emif = get_device_details(pdev); + if (!emif) { + pr_err("%s: error getting device data\n", __func__); + goto error; + } + + if (!emif1) + emif1 = emif; + + list_add(&emif->node, &device_list); + + /* Save pointers to each other in emif and device structures */ + emif->dev = &pdev->dev; + platform_set_drvdata(pdev, emif); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(emif->dev, "%s: error getting memory resource\n", + __func__); + goto error; + } + + emif->base = devm_request_and_ioremap(emif->dev, res); + if (!emif->base) { + dev_err(emif->dev, "%s: devm_request_and_ioremap() failed\n", + __func__); + goto error; + } + + dev_info(&pdev->dev, "%s: device configured with addr = %p\n", + __func__, emif->base); + + return 0; +error: + return -ENODEV; +} + +static struct platform_driver emif_driver = { + .driver = { + .name = "emif", + }, +}; + +static int __init_or_module emif_register(void) +{ + return platform_driver_probe(&emif_driver, emif_probe); +} + +static void __exit emif_unregister(void) +{ + platform_driver_unregister(&emif_driver); +} + +module_init(emif_register); +module_exit(emif_unregister); +MODULE_DESCRIPTION("TI EMIF SDRAM Controller Driver"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:emif"); +MODULE_AUTHOR("Texas Instruments Inc"); diff --git a/drivers/memory/emif.h b/drivers/memory/emif.h index 44b97dfe95b4..692b2a864e7b 100644 --- a/drivers/memory/emif.h +++ b/drivers/memory/emif.h @@ -12,6 +12,13 @@ #ifndef __EMIF_H #define __EMIF_H +/* + * Maximum number of different frequencies supported by EMIF driver + * Determines the number of entries in the pointer array for register + * cache + */ +#define EMIF_MAX_NUM_FREQUENCIES 6 + /* Registers offset */ #define EMIF_MODULE_ID_AND_REVISION 0x0000 #define EMIF_STATUS 0x0004 diff --git a/include/linux/platform_data/emif_plat.h b/include/linux/platform_data/emif_plat.h new file mode 100644 index 000000000000..03378ca84061 --- /dev/null +++ b/include/linux/platform_data/emif_plat.h @@ -0,0 +1,128 @@ +/* + * Definitions for TI EMIF device platform data + * + * Copyright (C) 2012 Texas Instruments, Inc. + * + * Aneesh V + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __EMIF_PLAT_H +#define __EMIF_PLAT_H + +/* Low power modes - EMIF_PWR_MGMT_CTRL */ +#define EMIF_LP_MODE_DISABLE 0 +#define EMIF_LP_MODE_CLOCK_STOP 1 +#define EMIF_LP_MODE_SELF_REFRESH 2 +#define EMIF_LP_MODE_PWR_DN 4 + +/* Hardware capabilities */ +#define EMIF_HW_CAPS_LL_INTERFACE 0x00000001 + +/* + * EMIF IP Revisions + * EMIF4D - Used in OMAP4 + * EMIF4D5 - Used in OMAP5 + */ +#define EMIF_4D 1 +#define EMIF_4D5 2 + +/* + * PHY types + * ATTILAPHY - Used in OMAP4 + * INTELLIPHY - Used in OMAP5 + */ +#define EMIF_PHY_TYPE_ATTILAPHY 1 +#define EMIF_PHY_TYPE_INTELLIPHY 2 + +/* Custom config requests */ +#define EMIF_CUSTOM_CONFIG_LPMODE 0x00000001 +#define EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL 0x00000002 + +#ifndef __ASSEMBLY__ +/** + * struct ddr_device_info - All information about the DDR device except AC + * timing parameters + * @type: Device type (LPDDR2-S4, LPDDR2-S2 etc) + * @density: Device density + * @io_width: Bus width + * @cs1_used: Whether there is a DDR device attached to the second + * chip-select(CS1) of this EMIF instance + * @cal_resistors_per_cs: Whether there is one calibration resistor per + * chip-select or whether it's a single one for both + * @manufacturer: Manufacturer name string + */ +struct ddr_device_info { + u32 type; + u32 density; + u32 io_width; + u32 cs1_used; + u32 cal_resistors_per_cs; + char manufacturer[10]; +}; + +/** + * struct emif_custom_configs - Custom configuration parameters/policies + * passed from the platform layer + * @mask: Mask to indicate which configs are requested + * @lpmode: LPMODE to be used in PWR_MGMT_CTRL register + * @lpmode_timeout_performance: Timeout before LPMODE entry when higher + * performance is desired at the cost of power (typically + * at higher OPPs) + * @lpmode_timeout_power: Timeout before LPMODE entry when better power + * savings is desired and performance is not important + * (typically at lower loads indicated by lower OPPs) + * @lpmode_freq_threshold: The DDR frequency threshold to identify between + * the above two cases: + * timeout = (freq >= lpmode_freq_threshold) ? + * lpmode_timeout_performance : + * lpmode_timeout_power; + * @temp_alert_poll_interval_ms: LPDDR2 MR4 polling interval at nominal + * temperature(in milliseconds). When temperature is high + * polling is done 4 times as frequently. + */ +struct emif_custom_configs { + u32 mask; + u32 lpmode; + u32 lpmode_timeout_performance; + u32 lpmode_timeout_power; + u32 lpmode_freq_threshold; + u32 temp_alert_poll_interval_ms; +}; + +/** + * struct emif_platform_data - Platform data passed on EMIF platform + * device creation. Used by the driver. + * @hw_caps: Hw capabilities of the EMIF IP in the respective SoC + * @device_info: Device info structure containing information such + * as type, bus width, density etc + * @timings: Timings information from device datasheet passed + * as an array of 'struct lpddr2_timings'. Can be NULL + * if if default timings are ok + * @timings_arr_size: Size of the timings array. Depends on the number + * of different frequencies for which timings data + * is provided + * @min_tck: Minimum value of some timing parameters in terms + * of number of cycles. Can be NULL if default values + * are ok + * @custom_configs: Custom configurations requested by SoC or board + * code and the data for them. Can be NULL if default + * configurations done by the driver are ok. See + * documentation for 'struct emif_custom_configs' for + * more details + */ +struct emif_platform_data { + u32 hw_caps; + struct ddr_device_info *device_info; + const struct lpddr2_timings *timings; + u32 timings_arr_size; + const struct lpddr2_min_tck *min_tck; + struct emif_custom_configs *custom_configs; + u32 ip_rev; + u32 phy_type; +}; +#endif /* __ASSEMBLY__ */ + +#endif /* __LINUX_EMIF_H */ -- cgit v1.2.3 From 127d42ae47703fe7b7bc59c0fb687a05e22a92a4 Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Fri, 4 May 2012 14:16:59 +0200 Subject: usb:hsotg:samsung: Remove platform dependency from s3c-hsotg This code removes platform dependency from s3c-hsotg driver. Signed-off-by: Lukasz Majewski Signed-off-by: Kyungmin Park Cc: Kukjin Kim Signed-off-by: Felipe Balbi --- arch/arm/mach-exynos/mach-nuri.c | 1 + arch/arm/mach-exynos/mach-universal_c210.c | 1 + arch/arm/mach-s3c64xx/mach-crag6410.c | 2 +- arch/arm/mach-s3c64xx/mach-smartq.c | 2 +- arch/arm/mach-s3c64xx/mach-smdk6410.c | 2 +- arch/arm/mach-s5pv210/mach-goni.c | 1 + arch/arm/plat-samsung/devs.c | 2 +- .../arm/plat-samsung/include/plat/regs-usb-hsotg.h | 379 --------------------- arch/arm/plat-samsung/include/plat/udc-hs.h | 34 -- drivers/usb/gadget/s3c-hsotg.c | 4 +- drivers/usb/gadget/s3c-hsotg.h | 379 +++++++++++++++++++++ include/linux/platform_data/s3c-hsotg.h | 35 ++ 12 files changed, 423 insertions(+), 419 deletions(-) delete mode 100644 arch/arm/plat-samsung/include/plat/regs-usb-hsotg.h delete mode 100644 arch/arm/plat-samsung/include/plat/udc-hs.h create mode 100644 drivers/usb/gadget/s3c-hsotg.h create mode 100644 include/linux/platform_data/s3c-hsotg.h (limited to 'include/linux/platform_data') diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c index b4f1f902ce6d..e284b0e4ca2e 100644 --- a/arch/arm/mach-exynos/mach-nuri.c +++ b/arch/arm/mach-exynos/mach-nuri.c @@ -44,6 +44,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c index 7ebf79c2ab34..ad15d0fda3c1 100644 --- a/arch/arm/mach-exynos/mach-universal_c210.c +++ b/arch/arm/mach-exynos/mach-universal_c210.c @@ -42,6 +42,7 @@ #include #include #include +#include #include diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c index e20bf5835365..a02f204d99ed 100644 --- a/arch/arm/mach-s3c64xx/mach-crag6410.c +++ b/arch/arm/mach-s3c64xx/mach-crag6410.c @@ -61,7 +61,7 @@ #include #include #include -#include +#include #include #include diff --git a/arch/arm/mach-s3c64xx/mach-smartq.c b/arch/arm/mach-s3c64xx/mach-smartq.c index ce745e19aa27..ee0d13c98378 100644 --- a/arch/arm/mach-s3c64xx/mach-smartq.c +++ b/arch/arm/mach-s3c64xx/mach-smartq.c @@ -33,7 +33,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c index d55bc96d9582..bf477e33f0ee 100644 --- a/arch/arm/mach-s3c64xx/mach-smdk6410.c +++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c @@ -72,7 +72,7 @@ #include #include #include -#include +#include #include "common.h" diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c index a8933de3d627..921da285ff20 100644 --- a/arch/arm/mach-s5pv210/mach-goni.c +++ b/arch/arm/mach-s5pv210/mach-goni.c @@ -49,6 +49,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c index 8b928f9bc1c3..a41c808847c0 100644 --- a/arch/arm/plat-samsung/devs.c +++ b/arch/arm/plat-samsung/devs.c @@ -57,7 +57,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/plat-samsung/include/plat/regs-usb-hsotg.h b/arch/arm/plat-samsung/include/plat/regs-usb-hsotg.h deleted file mode 100644 index dc90f5ede88f..000000000000 --- a/arch/arm/plat-samsung/include/plat/regs-usb-hsotg.h +++ /dev/null @@ -1,379 +0,0 @@ -/* arch/arm/plat-s3c/include/plat/regs-usb-hsotg.h - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks - * - * S3C - USB2.0 Highspeed/OtG device block registers - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __PLAT_S3C64XX_REGS_USB_HSOTG_H -#define __PLAT_S3C64XX_REGS_USB_HSOTG_H __FILE__ - -#define S3C_HSOTG_REG(x) (x) - -#define S3C_GOTGCTL S3C_HSOTG_REG(0x000) -#define S3C_GOTGCTL_BSESVLD (1 << 19) -#define S3C_GOTGCTL_ASESVLD (1 << 18) -#define S3C_GOTGCTL_DBNC_SHORT (1 << 17) -#define S3C_GOTGCTL_CONID_B (1 << 16) -#define S3C_GOTGCTL_DEVHNPEN (1 << 11) -#define S3C_GOTGCTL_HSSETHNPEN (1 << 10) -#define S3C_GOTGCTL_HNPREQ (1 << 9) -#define S3C_GOTGCTL_HSTNEGSCS (1 << 8) -#define S3C_GOTGCTL_SESREQ (1 << 1) -#define S3C_GOTGCTL_SESREQSCS (1 << 0) - -#define S3C_GOTGINT S3C_HSOTG_REG(0x004) -#define S3C_GOTGINT_DbnceDone (1 << 19) -#define S3C_GOTGINT_ADevTOUTChg (1 << 18) -#define S3C_GOTGINT_HstNegDet (1 << 17) -#define S3C_GOTGINT_HstnegSucStsChng (1 << 9) -#define S3C_GOTGINT_SesReqSucStsChng (1 << 8) -#define S3C_GOTGINT_SesEndDet (1 << 2) - -#define S3C_GAHBCFG S3C_HSOTG_REG(0x008) -#define S3C_GAHBCFG_PTxFEmpLvl (1 << 8) -#define S3C_GAHBCFG_NPTxFEmpLvl (1 << 7) -#define S3C_GAHBCFG_DMAEn (1 << 5) -#define S3C_GAHBCFG_HBstLen_MASK (0xf << 1) -#define S3C_GAHBCFG_HBstLen_SHIFT (1) -#define S3C_GAHBCFG_HBstLen_Single (0x0 << 1) -#define S3C_GAHBCFG_HBstLen_Incr (0x1 << 1) -#define S3C_GAHBCFG_HBstLen_Incr4 (0x3 << 1) -#define S3C_GAHBCFG_HBstLen_Incr8 (0x5 << 1) -#define S3C_GAHBCFG_HBstLen_Incr16 (0x7 << 1) -#define S3C_GAHBCFG_GlblIntrEn (1 << 0) - -#define S3C_GUSBCFG S3C_HSOTG_REG(0x00C) -#define S3C_GUSBCFG_PHYLPClkSel (1 << 15) -#define S3C_GUSBCFG_HNPCap (1 << 9) -#define S3C_GUSBCFG_SRPCap (1 << 8) -#define S3C_GUSBCFG_PHYIf16 (1 << 3) -#define S3C_GUSBCFG_TOutCal_MASK (0x7 << 0) -#define S3C_GUSBCFG_TOutCal_SHIFT (0) -#define S3C_GUSBCFG_TOutCal_LIMIT (0x7) -#define S3C_GUSBCFG_TOutCal(_x) ((_x) << 0) - -#define S3C_GRSTCTL S3C_HSOTG_REG(0x010) - -#define S3C_GRSTCTL_AHBIdle (1 << 31) -#define S3C_GRSTCTL_DMAReq (1 << 30) -#define S3C_GRSTCTL_TxFNum_MASK (0x1f << 6) -#define S3C_GRSTCTL_TxFNum_SHIFT (6) -#define S3C_GRSTCTL_TxFNum_LIMIT (0x1f) -#define S3C_GRSTCTL_TxFNum(_x) ((_x) << 6) -#define S3C_GRSTCTL_TxFFlsh (1 << 5) -#define S3C_GRSTCTL_RxFFlsh (1 << 4) -#define S3C_GRSTCTL_INTknQFlsh (1 << 3) -#define S3C_GRSTCTL_FrmCntrRst (1 << 2) -#define S3C_GRSTCTL_HSftRst (1 << 1) -#define S3C_GRSTCTL_CSftRst (1 << 0) - -#define S3C_GINTSTS S3C_HSOTG_REG(0x014) -#define S3C_GINTMSK S3C_HSOTG_REG(0x018) - -#define S3C_GINTSTS_WkUpInt (1 << 31) -#define S3C_GINTSTS_SessReqInt (1 << 30) -#define S3C_GINTSTS_DisconnInt (1 << 29) -#define S3C_GINTSTS_ConIDStsChng (1 << 28) -#define S3C_GINTSTS_PTxFEmp (1 << 26) -#define S3C_GINTSTS_HChInt (1 << 25) -#define S3C_GINTSTS_PrtInt (1 << 24) -#define S3C_GINTSTS_FetSusp (1 << 22) -#define S3C_GINTSTS_incompIP (1 << 21) -#define S3C_GINTSTS_IncomplSOIN (1 << 20) -#define S3C_GINTSTS_OEPInt (1 << 19) -#define S3C_GINTSTS_IEPInt (1 << 18) -#define S3C_GINTSTS_EPMis (1 << 17) -#define S3C_GINTSTS_EOPF (1 << 15) -#define S3C_GINTSTS_ISOutDrop (1 << 14) -#define S3C_GINTSTS_EnumDone (1 << 13) -#define S3C_GINTSTS_USBRst (1 << 12) -#define S3C_GINTSTS_USBSusp (1 << 11) -#define S3C_GINTSTS_ErlySusp (1 << 10) -#define S3C_GINTSTS_GOUTNakEff (1 << 7) -#define S3C_GINTSTS_GINNakEff (1 << 6) -#define S3C_GINTSTS_NPTxFEmp (1 << 5) -#define S3C_GINTSTS_RxFLvl (1 << 4) -#define S3C_GINTSTS_SOF (1 << 3) -#define S3C_GINTSTS_OTGInt (1 << 2) -#define S3C_GINTSTS_ModeMis (1 << 1) -#define S3C_GINTSTS_CurMod_Host (1 << 0) - -#define S3C_GRXSTSR S3C_HSOTG_REG(0x01C) -#define S3C_GRXSTSP S3C_HSOTG_REG(0x020) - -#define S3C_GRXSTS_FN_MASK (0x7f << 25) -#define S3C_GRXSTS_FN_SHIFT (25) - -#define S3C_GRXSTS_PktSts_MASK (0xf << 17) -#define S3C_GRXSTS_PktSts_SHIFT (17) -#define S3C_GRXSTS_PktSts_GlobalOutNAK (0x1 << 17) -#define S3C_GRXSTS_PktSts_OutRX (0x2 << 17) -#define S3C_GRXSTS_PktSts_OutDone (0x3 << 17) -#define S3C_GRXSTS_PktSts_SetupDone (0x4 << 17) -#define S3C_GRXSTS_PktSts_SetupRX (0x6 << 17) - -#define S3C_GRXSTS_DPID_MASK (0x3 << 15) -#define S3C_GRXSTS_DPID_SHIFT (15) -#define S3C_GRXSTS_ByteCnt_MASK (0x7ff << 4) -#define S3C_GRXSTS_ByteCnt_SHIFT (4) -#define S3C_GRXSTS_EPNum_MASK (0xf << 0) -#define S3C_GRXSTS_EPNum_SHIFT (0) - -#define S3C_GRXFSIZ S3C_HSOTG_REG(0x024) - -#define S3C_GNPTXFSIZ S3C_HSOTG_REG(0x028) - -#define S3C_GNPTXFSIZ_NPTxFDep_MASK (0xffff << 16) -#define S3C_GNPTXFSIZ_NPTxFDep_SHIFT (16) -#define S3C_GNPTXFSIZ_NPTxFDep_LIMIT (0xffff) -#define S3C_GNPTXFSIZ_NPTxFDep(_x) ((_x) << 16) -#define S3C_GNPTXFSIZ_NPTxFStAddr_MASK (0xffff << 0) -#define S3C_GNPTXFSIZ_NPTxFStAddr_SHIFT (0) -#define S3C_GNPTXFSIZ_NPTxFStAddr_LIMIT (0xffff) -#define S3C_GNPTXFSIZ_NPTxFStAddr(_x) ((_x) << 0) - -#define S3C_GNPTXSTS S3C_HSOTG_REG(0x02C) - -#define S3C_GNPTXSTS_NPtxQTop_MASK (0x7f << 24) -#define S3C_GNPTXSTS_NPtxQTop_SHIFT (24) - -#define S3C_GNPTXSTS_NPTxQSpcAvail_MASK (0xff << 16) -#define S3C_GNPTXSTS_NPTxQSpcAvail_SHIFT (16) -#define S3C_GNPTXSTS_NPTxQSpcAvail_GET(_v) (((_v) >> 16) & 0xff) - -#define S3C_GNPTXSTS_NPTxFSpcAvail_MASK (0xffff << 0) -#define S3C_GNPTXSTS_NPTxFSpcAvail_SHIFT (0) -#define S3C_GNPTXSTS_NPTxFSpcAvail_GET(_v) (((_v) >> 0) & 0xffff) - - -#define S3C_HPTXFSIZ S3C_HSOTG_REG(0x100) - -#define S3C_DPTXFSIZn(_a) S3C_HSOTG_REG(0x104 + (((_a) - 1) * 4)) - -#define S3C_DPTXFSIZn_DPTxFSize_MASK (0xffff << 16) -#define S3C_DPTXFSIZn_DPTxFSize_SHIFT (16) -#define S3C_DPTXFSIZn_DPTxFSize_GET(_v) (((_v) >> 16) & 0xffff) -#define S3C_DPTXFSIZn_DPTxFSize_LIMIT (0xffff) -#define S3C_DPTXFSIZn_DPTxFSize(_x) ((_x) << 16) - -#define S3C_DPTXFSIZn_DPTxFStAddr_MASK (0xffff << 0) -#define S3C_DPTXFSIZn_DPTxFStAddr_SHIFT (0) - -/* Device mode registers */ -#define S3C_DCFG S3C_HSOTG_REG(0x800) - -#define S3C_DCFG_EPMisCnt_MASK (0x1f << 18) -#define S3C_DCFG_EPMisCnt_SHIFT (18) -#define S3C_DCFG_EPMisCnt_LIMIT (0x1f) -#define S3C_DCFG_EPMisCnt(_x) ((_x) << 18) - -#define S3C_DCFG_PerFrInt_MASK (0x3 << 11) -#define S3C_DCFG_PerFrInt_SHIFT (11) -#define S3C_DCFG_PerFrInt_LIMIT (0x3) -#define S3C_DCFG_PerFrInt(_x) ((_x) << 11) - -#define S3C_DCFG_DevAddr_MASK (0x7f << 4) -#define S3C_DCFG_DevAddr_SHIFT (4) -#define S3C_DCFG_DevAddr_LIMIT (0x7f) -#define S3C_DCFG_DevAddr(_x) ((_x) << 4) - -#define S3C_DCFG_NZStsOUTHShk (1 << 2) - -#define S3C_DCFG_DevSpd_MASK (0x3 << 0) -#define S3C_DCFG_DevSpd_SHIFT (0) -#define S3C_DCFG_DevSpd_HS (0x0 << 0) -#define S3C_DCFG_DevSpd_FS (0x1 << 0) -#define S3C_DCFG_DevSpd_LS (0x2 << 0) -#define S3C_DCFG_DevSpd_FS48 (0x3 << 0) - -#define S3C_DCTL S3C_HSOTG_REG(0x804) - -#define S3C_DCTL_PWROnPrgDone (1 << 11) -#define S3C_DCTL_CGOUTNak (1 << 10) -#define S3C_DCTL_SGOUTNak (1 << 9) -#define S3C_DCTL_CGNPInNAK (1 << 8) -#define S3C_DCTL_SGNPInNAK (1 << 7) -#define S3C_DCTL_TstCtl_MASK (0x7 << 4) -#define S3C_DCTL_TstCtl_SHIFT (4) -#define S3C_DCTL_GOUTNakSts (1 << 3) -#define S3C_DCTL_GNPINNakSts (1 << 2) -#define S3C_DCTL_SftDiscon (1 << 1) -#define S3C_DCTL_RmtWkUpSig (1 << 0) - -#define S3C_DSTS S3C_HSOTG_REG(0x808) - -#define S3C_DSTS_SOFFN_MASK (0x3fff << 8) -#define S3C_DSTS_SOFFN_SHIFT (8) -#define S3C_DSTS_SOFFN_LIMIT (0x3fff) -#define S3C_DSTS_SOFFN(_x) ((_x) << 8) -#define S3C_DSTS_ErraticErr (1 << 3) -#define S3C_DSTS_EnumSpd_MASK (0x3 << 1) -#define S3C_DSTS_EnumSpd_SHIFT (1) -#define S3C_DSTS_EnumSpd_HS (0x0 << 1) -#define S3C_DSTS_EnumSpd_FS (0x1 << 1) -#define S3C_DSTS_EnumSpd_LS (0x2 << 1) -#define S3C_DSTS_EnumSpd_FS48 (0x3 << 1) - -#define S3C_DSTS_SuspSts (1 << 0) - -#define S3C_DIEPMSK S3C_HSOTG_REG(0x810) - -#define S3C_DIEPMSK_TxFIFOEmpty (1 << 7) -#define S3C_DIEPMSK_INEPNakEffMsk (1 << 6) -#define S3C_DIEPMSK_INTknEPMisMsk (1 << 5) -#define S3C_DIEPMSK_INTknTXFEmpMsk (1 << 4) -#define S3C_DIEPMSK_TimeOUTMsk (1 << 3) -#define S3C_DIEPMSK_AHBErrMsk (1 << 2) -#define S3C_DIEPMSK_EPDisbldMsk (1 << 1) -#define S3C_DIEPMSK_XferComplMsk (1 << 0) - -#define S3C_DOEPMSK S3C_HSOTG_REG(0x814) - -#define S3C_DOEPMSK_Back2BackSetup (1 << 6) -#define S3C_DOEPMSK_OUTTknEPdisMsk (1 << 4) -#define S3C_DOEPMSK_SetupMsk (1 << 3) -#define S3C_DOEPMSK_AHBErrMsk (1 << 2) -#define S3C_DOEPMSK_EPDisbldMsk (1 << 1) -#define S3C_DOEPMSK_XferComplMsk (1 << 0) - -#define S3C_DAINT S3C_HSOTG_REG(0x818) -#define S3C_DAINTMSK S3C_HSOTG_REG(0x81C) - -#define S3C_DAINT_OutEP_SHIFT (16) -#define S3C_DAINT_OutEP(x) (1 << ((x) + 16)) -#define S3C_DAINT_InEP(x) (1 << (x)) - -#define S3C_DTKNQR1 S3C_HSOTG_REG(0x820) -#define S3C_DTKNQR2 S3C_HSOTG_REG(0x824) -#define S3C_DTKNQR3 S3C_HSOTG_REG(0x830) -#define S3C_DTKNQR4 S3C_HSOTG_REG(0x834) - -#define S3C_DVBUSDIS S3C_HSOTG_REG(0x828) -#define S3C_DVBUSPULSE S3C_HSOTG_REG(0x82C) - -#define S3C_DIEPCTL0 S3C_HSOTG_REG(0x900) -#define S3C_DOEPCTL0 S3C_HSOTG_REG(0xB00) -#define S3C_DIEPCTL(_a) S3C_HSOTG_REG(0x900 + ((_a) * 0x20)) -#define S3C_DOEPCTL(_a) S3C_HSOTG_REG(0xB00 + ((_a) * 0x20)) - -/* EP0 specialness: - * bits[29..28] - reserved (no SetD0PID, SetD1PID) - * bits[25..22] - should always be zero, this isn't a periodic endpoint - * bits[10..0] - MPS setting differenct for EP0 -*/ -#define S3C_D0EPCTL_MPS_MASK (0x3 << 0) -#define S3C_D0EPCTL_MPS_SHIFT (0) -#define S3C_D0EPCTL_MPS_64 (0x0 << 0) -#define S3C_D0EPCTL_MPS_32 (0x1 << 0) -#define S3C_D0EPCTL_MPS_16 (0x2 << 0) -#define S3C_D0EPCTL_MPS_8 (0x3 << 0) - -#define S3C_DxEPCTL_EPEna (1 << 31) -#define S3C_DxEPCTL_EPDis (1 << 30) -#define S3C_DxEPCTL_SetD1PID (1 << 29) -#define S3C_DxEPCTL_SetOddFr (1 << 29) -#define S3C_DxEPCTL_SetD0PID (1 << 28) -#define S3C_DxEPCTL_SetEvenFr (1 << 28) -#define S3C_DxEPCTL_SNAK (1 << 27) -#define S3C_DxEPCTL_CNAK (1 << 26) -#define S3C_DxEPCTL_TxFNum_MASK (0xf << 22) -#define S3C_DxEPCTL_TxFNum_SHIFT (22) -#define S3C_DxEPCTL_TxFNum_LIMIT (0xf) -#define S3C_DxEPCTL_TxFNum(_x) ((_x) << 22) - -#define S3C_DxEPCTL_Stall (1 << 21) -#define S3C_DxEPCTL_Snp (1 << 20) -#define S3C_DxEPCTL_EPType_MASK (0x3 << 18) -#define S3C_DxEPCTL_EPType_SHIFT (18) -#define S3C_DxEPCTL_EPType_Control (0x0 << 18) -#define S3C_DxEPCTL_EPType_Iso (0x1 << 18) -#define S3C_DxEPCTL_EPType_Bulk (0x2 << 18) -#define S3C_DxEPCTL_EPType_Intterupt (0x3 << 18) - -#define S3C_DxEPCTL_NAKsts (1 << 17) -#define S3C_DxEPCTL_DPID (1 << 16) -#define S3C_DxEPCTL_EOFrNum (1 << 16) -#define S3C_DxEPCTL_USBActEp (1 << 15) -#define S3C_DxEPCTL_NextEp_MASK (0xf << 11) -#define S3C_DxEPCTL_NextEp_SHIFT (11) -#define S3C_DxEPCTL_NextEp_LIMIT (0xf) -#define S3C_DxEPCTL_NextEp(_x) ((_x) << 11) - -#define S3C_DxEPCTL_MPS_MASK (0x7ff << 0) -#define S3C_DxEPCTL_MPS_SHIFT (0) -#define S3C_DxEPCTL_MPS_LIMIT (0x7ff) -#define S3C_DxEPCTL_MPS(_x) ((_x) << 0) - -#define S3C_DIEPINT(_a) S3C_HSOTG_REG(0x908 + ((_a) * 0x20)) -#define S3C_DOEPINT(_a) S3C_HSOTG_REG(0xB08 + ((_a) * 0x20)) - -#define S3C_DxEPINT_INEPNakEff (1 << 6) -#define S3C_DxEPINT_Back2BackSetup (1 << 6) -#define S3C_DxEPINT_INTknEPMis (1 << 5) -#define S3C_DxEPINT_INTknTXFEmp (1 << 4) -#define S3C_DxEPINT_OUTTknEPdis (1 << 4) -#define S3C_DxEPINT_Timeout (1 << 3) -#define S3C_DxEPINT_Setup (1 << 3) -#define S3C_DxEPINT_AHBErr (1 << 2) -#define S3C_DxEPINT_EPDisbld (1 << 1) -#define S3C_DxEPINT_XferCompl (1 << 0) - -#define S3C_DIEPTSIZ0 S3C_HSOTG_REG(0x910) - -#define S3C_DIEPTSIZ0_PktCnt_MASK (0x3 << 19) -#define S3C_DIEPTSIZ0_PktCnt_SHIFT (19) -#define S3C_DIEPTSIZ0_PktCnt_LIMIT (0x3) -#define S3C_DIEPTSIZ0_PktCnt(_x) ((_x) << 19) - -#define S3C_DIEPTSIZ0_XferSize_MASK (0x7f << 0) -#define S3C_DIEPTSIZ0_XferSize_SHIFT (0) -#define S3C_DIEPTSIZ0_XferSize_LIMIT (0x7f) -#define S3C_DIEPTSIZ0_XferSize(_x) ((_x) << 0) - - -#define DOEPTSIZ0 S3C_HSOTG_REG(0xB10) -#define S3C_DOEPTSIZ0_SUPCnt_MASK (0x3 << 29) -#define S3C_DOEPTSIZ0_SUPCnt_SHIFT (29) -#define S3C_DOEPTSIZ0_SUPCnt_LIMIT (0x3) -#define S3C_DOEPTSIZ0_SUPCnt(_x) ((_x) << 29) - -#define S3C_DOEPTSIZ0_PktCnt (1 << 19) -#define S3C_DOEPTSIZ0_XferSize_MASK (0x7f << 0) -#define S3C_DOEPTSIZ0_XferSize_SHIFT (0) - -#define S3C_DIEPTSIZ(_a) S3C_HSOTG_REG(0x910 + ((_a) * 0x20)) -#define S3C_DOEPTSIZ(_a) S3C_HSOTG_REG(0xB10 + ((_a) * 0x20)) - -#define S3C_DxEPTSIZ_MC_MASK (0x3 << 29) -#define S3C_DxEPTSIZ_MC_SHIFT (29) -#define S3C_DxEPTSIZ_MC_LIMIT (0x3) -#define S3C_DxEPTSIZ_MC(_x) ((_x) << 29) - -#define S3C_DxEPTSIZ_PktCnt_MASK (0x3ff << 19) -#define S3C_DxEPTSIZ_PktCnt_SHIFT (19) -#define S3C_DxEPTSIZ_PktCnt_GET(_v) (((_v) >> 19) & 0x3ff) -#define S3C_DxEPTSIZ_PktCnt_LIMIT (0x3ff) -#define S3C_DxEPTSIZ_PktCnt(_x) ((_x) << 19) - -#define S3C_DxEPTSIZ_XferSize_MASK (0x7ffff << 0) -#define S3C_DxEPTSIZ_XferSize_SHIFT (0) -#define S3C_DxEPTSIZ_XferSize_GET(_v) (((_v) >> 0) & 0x7ffff) -#define S3C_DxEPTSIZ_XferSize_LIMIT (0x7ffff) -#define S3C_DxEPTSIZ_XferSize(_x) ((_x) << 0) - - -#define S3C_DIEPDMA(_a) S3C_HSOTG_REG(0x914 + ((_a) * 0x20)) -#define S3C_DOEPDMA(_a) S3C_HSOTG_REG(0xB14 + ((_a) * 0x20)) -#define S3C_DTXFSTS(_a) S3C_HSOTG_REG(0x918 + ((_a) * 0x20)) - -#define S3C_EPFIFO(_a) S3C_HSOTG_REG(0x1000 + ((_a) * 0x1000)) - -#endif /* __PLAT_S3C64XX_REGS_USB_HSOTG_H */ diff --git a/arch/arm/plat-samsung/include/plat/udc-hs.h b/arch/arm/plat-samsung/include/plat/udc-hs.h deleted file mode 100644 index c9e3667cb2b1..000000000000 --- a/arch/arm/plat-samsung/include/plat/udc-hs.h +++ /dev/null @@ -1,34 +0,0 @@ -/* arch/arm/plat-s3c/include/plat/udc-hs.h - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks - * http://armlinux.simtec.co.uk/ - * - * S3C USB2.0 High-speed / OtG platform information - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -enum s3c_hsotg_dmamode { - S3C_HSOTG_DMA_NONE, /* do not use DMA at-all */ - S3C_HSOTG_DMA_ONLY, /* always use DMA */ - S3C_HSOTG_DMA_DRV, /* DMA is chosen by driver */ -}; - -/** - * struct s3c_hsotg_plat - platform data for high-speed otg/udc - * @dma: Whether to use DMA or not. - * @is_osc: The clock source is an oscillator, not a crystal - */ -struct s3c_hsotg_plat { - enum s3c_hsotg_dmamode dma; - unsigned int is_osc : 1; - - int (*phy_init)(struct platform_device *pdev, int type); - int (*phy_exit)(struct platform_device *pdev, int type); -}; - -extern void s3c_hsotg_set_platdata(struct s3c_hsotg_plat *pd); diff --git a/drivers/usb/gadget/s3c-hsotg.c b/drivers/usb/gadget/s3c-hsotg.c index 105b206cd844..70c6f3b45cf2 100644 --- a/drivers/usb/gadget/s3c-hsotg.c +++ b/drivers/usb/gadget/s3c-hsotg.c @@ -34,9 +34,9 @@ #include #include -#include +#include "s3c-hsotg.h" +#include #include -#include #include #define DMA_ADDR_INVALID (~((dma_addr_t)0)) diff --git a/drivers/usb/gadget/s3c-hsotg.h b/drivers/usb/gadget/s3c-hsotg.h new file mode 100644 index 000000000000..4c4ccc44b577 --- /dev/null +++ b/drivers/usb/gadget/s3c-hsotg.h @@ -0,0 +1,379 @@ +/* arch/arm/plat-s3c/include/plat/regs-usb-hsotg.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks + * + * S3C - USB2.0 Highspeed/OtG device block registers + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __PLAT_S3C64XX_REGS_USB_HSOTG_H +#define __PLAT_S3C64XX_REGS_USB_HSOTG_H __FILE__ + +#define S3C_HSOTG_REG(x) (x) + +#define S3C_GOTGCTL S3C_HSOTG_REG(0x000) +#define S3C_GOTGCTL_BSESVLD (1 << 19) +#define S3C_GOTGCTL_ASESVLD (1 << 18) +#define S3C_GOTGCTL_DBNC_SHORT (1 << 17) +#define S3C_GOTGCTL_CONID_B (1 << 16) +#define S3C_GOTGCTL_DEVHNPEN (1 << 11) +#define S3C_GOTGCTL_HSSETHNPEN (1 << 10) +#define S3C_GOTGCTL_HNPREQ (1 << 9) +#define S3C_GOTGCTL_HSTNEGSCS (1 << 8) +#define S3C_GOTGCTL_SESREQ (1 << 1) +#define S3C_GOTGCTL_SESREQSCS (1 << 0) + +#define S3C_GOTGINT S3C_HSOTG_REG(0x004) +#define S3C_GOTGINT_DbnceDone (1 << 19) +#define S3C_GOTGINT_ADevTOUTChg (1 << 18) +#define S3C_GOTGINT_HstNegDet (1 << 17) +#define S3C_GOTGINT_HstnegSucStsChng (1 << 9) +#define S3C_GOTGINT_SesReqSucStsChng (1 << 8) +#define S3C_GOTGINT_SesEndDet (1 << 2) + +#define S3C_GAHBCFG S3C_HSOTG_REG(0x008) +#define S3C_GAHBCFG_PTxFEmpLvl (1 << 8) +#define S3C_GAHBCFG_NPTxFEmpLvl (1 << 7) +#define S3C_GAHBCFG_DMAEn (1 << 5) +#define S3C_GAHBCFG_HBstLen_MASK (0xf << 1) +#define S3C_GAHBCFG_HBstLen_SHIFT (1) +#define S3C_GAHBCFG_HBstLen_Single (0x0 << 1) +#define S3C_GAHBCFG_HBstLen_Incr (0x1 << 1) +#define S3C_GAHBCFG_HBstLen_Incr4 (0x3 << 1) +#define S3C_GAHBCFG_HBstLen_Incr8 (0x5 << 1) +#define S3C_GAHBCFG_HBstLen_Incr16 (0x7 << 1) +#define S3C_GAHBCFG_GlblIntrEn (1 << 0) + +#define S3C_GUSBCFG S3C_HSOTG_REG(0x00C) +#define S3C_GUSBCFG_PHYLPClkSel (1 << 15) +#define S3C_GUSBCFG_HNPCap (1 << 9) +#define S3C_GUSBCFG_SRPCap (1 << 8) +#define S3C_GUSBCFG_PHYIf16 (1 << 3) +#define S3C_GUSBCFG_TOutCal_MASK (0x7 << 0) +#define S3C_GUSBCFG_TOutCal_SHIFT (0) +#define S3C_GUSBCFG_TOutCal_LIMIT (0x7) +#define S3C_GUSBCFG_TOutCal(_x) ((_x) << 0) + +#define S3C_GRSTCTL S3C_HSOTG_REG(0x010) + +#define S3C_GRSTCTL_AHBIdle (1 << 31) +#define S3C_GRSTCTL_DMAReq (1 << 30) +#define S3C_GRSTCTL_TxFNum_MASK (0x1f << 6) +#define S3C_GRSTCTL_TxFNum_SHIFT (6) +#define S3C_GRSTCTL_TxFNum_LIMIT (0x1f) +#define S3C_GRSTCTL_TxFNum(_x) ((_x) << 6) +#define S3C_GRSTCTL_TxFFlsh (1 << 5) +#define S3C_GRSTCTL_RxFFlsh (1 << 4) +#define S3C_GRSTCTL_INTknQFlsh (1 << 3) +#define S3C_GRSTCTL_FrmCntrRst (1 << 2) +#define S3C_GRSTCTL_HSftRst (1 << 1) +#define S3C_GRSTCTL_CSftRst (1 << 0) + +#define S3C_GINTSTS S3C_HSOTG_REG(0x014) +#define S3C_GINTMSK S3C_HSOTG_REG(0x018) + +#define S3C_GINTSTS_WkUpInt (1 << 31) +#define S3C_GINTSTS_SessReqInt (1 << 30) +#define S3C_GINTSTS_DisconnInt (1 << 29) +#define S3C_GINTSTS_ConIDStsChng (1 << 28) +#define S3C_GINTSTS_PTxFEmp (1 << 26) +#define S3C_GINTSTS_HChInt (1 << 25) +#define S3C_GINTSTS_PrtInt (1 << 24) +#define S3C_GINTSTS_FetSusp (1 << 22) +#define S3C_GINTSTS_incompIP (1 << 21) +#define S3C_GINTSTS_IncomplSOIN (1 << 20) +#define S3C_GINTSTS_OEPInt (1 << 19) +#define S3C_GINTSTS_IEPInt (1 << 18) +#define S3C_GINTSTS_EPMis (1 << 17) +#define S3C_GINTSTS_EOPF (1 << 15) +#define S3C_GINTSTS_ISOutDrop (1 << 14) +#define S3C_GINTSTS_EnumDone (1 << 13) +#define S3C_GINTSTS_USBRst (1 << 12) +#define S3C_GINTSTS_USBSusp (1 << 11) +#define S3C_GINTSTS_ErlySusp (1 << 10) +#define S3C_GINTSTS_GOUTNakEff (1 << 7) +#define S3C_GINTSTS_GINNakEff (1 << 6) +#define S3C_GINTSTS_NPTxFEmp (1 << 5) +#define S3C_GINTSTS_RxFLvl (1 << 4) +#define S3C_GINTSTS_SOF (1 << 3) +#define S3C_GINTSTS_OTGInt (1 << 2) +#define S3C_GINTSTS_ModeMis (1 << 1) +#define S3C_GINTSTS_CurMod_Host (1 << 0) + +#define S3C_GRXSTSR S3C_HSOTG_REG(0x01C) +#define S3C_GRXSTSP S3C_HSOTG_REG(0x020) + +#define S3C_GRXSTS_FN_MASK (0x7f << 25) +#define S3C_GRXSTS_FN_SHIFT (25) + +#define S3C_GRXSTS_PktSts_MASK (0xf << 17) +#define S3C_GRXSTS_PktSts_SHIFT (17) +#define S3C_GRXSTS_PktSts_GlobalOutNAK (0x1 << 17) +#define S3C_GRXSTS_PktSts_OutRX (0x2 << 17) +#define S3C_GRXSTS_PktSts_OutDone (0x3 << 17) +#define S3C_GRXSTS_PktSts_SetupDone (0x4 << 17) +#define S3C_GRXSTS_PktSts_SetupRX (0x6 << 17) + +#define S3C_GRXSTS_DPID_MASK (0x3 << 15) +#define S3C_GRXSTS_DPID_SHIFT (15) +#define S3C_GRXSTS_ByteCnt_MASK (0x7ff << 4) +#define S3C_GRXSTS_ByteCnt_SHIFT (4) +#define S3C_GRXSTS_EPNum_MASK (0xf << 0) +#define S3C_GRXSTS_EPNum_SHIFT (0) + +#define S3C_GRXFSIZ S3C_HSOTG_REG(0x024) + +#define S3C_GNPTXFSIZ S3C_HSOTG_REG(0x028) + +#define S3C_GNPTXFSIZ_NPTxFDep_MASK (0xffff << 16) +#define S3C_GNPTXFSIZ_NPTxFDep_SHIFT (16) +#define S3C_GNPTXFSIZ_NPTxFDep_LIMIT (0xffff) +#define S3C_GNPTXFSIZ_NPTxFDep(_x) ((_x) << 16) +#define S3C_GNPTXFSIZ_NPTxFStAddr_MASK (0xffff << 0) +#define S3C_GNPTXFSIZ_NPTxFStAddr_SHIFT (0) +#define S3C_GNPTXFSIZ_NPTxFStAddr_LIMIT (0xffff) +#define S3C_GNPTXFSIZ_NPTxFStAddr(_x) ((_x) << 0) + +#define S3C_GNPTXSTS S3C_HSOTG_REG(0x02C) + +#define S3C_GNPTXSTS_NPtxQTop_MASK (0x7f << 24) +#define S3C_GNPTXSTS_NPtxQTop_SHIFT (24) + +#define S3C_GNPTXSTS_NPTxQSpcAvail_MASK (0xff << 16) +#define S3C_GNPTXSTS_NPTxQSpcAvail_SHIFT (16) +#define S3C_GNPTXSTS_NPTxQSpcAvail_GET(_v) (((_v) >> 16) & 0xff) + +#define S3C_GNPTXSTS_NPTxFSpcAvail_MASK (0xffff << 0) +#define S3C_GNPTXSTS_NPTxFSpcAvail_SHIFT (0) +#define S3C_GNPTXSTS_NPTxFSpcAvail_GET(_v) (((_v) >> 0) & 0xffff) + + +#define S3C_HPTXFSIZ S3C_HSOTG_REG(0x100) + +#define S3C_DPTXFSIZn(_a) S3C_HSOTG_REG(0x104 + (((_a) - 1) * 4)) + +#define S3C_DPTXFSIZn_DPTxFSize_MASK (0xffff << 16) +#define S3C_DPTXFSIZn_DPTxFSize_SHIFT (16) +#define S3C_DPTXFSIZn_DPTxFSize_GET(_v) (((_v) >> 16) & 0xffff) +#define S3C_DPTXFSIZn_DPTxFSize_LIMIT (0xffff) +#define S3C_DPTXFSIZn_DPTxFSize(_x) ((_x) << 16) + +#define S3C_DPTXFSIZn_DPTxFStAddr_MASK (0xffff << 0) +#define S3C_DPTXFSIZn_DPTxFStAddr_SHIFT (0) + +/* Device mode registers */ +#define S3C_DCFG S3C_HSOTG_REG(0x800) + +#define S3C_DCFG_EPMisCnt_MASK (0x1f << 18) +#define S3C_DCFG_EPMisCnt_SHIFT (18) +#define S3C_DCFG_EPMisCnt_LIMIT (0x1f) +#define S3C_DCFG_EPMisCnt(_x) ((_x) << 18) + +#define S3C_DCFG_PerFrInt_MASK (0x3 << 11) +#define S3C_DCFG_PerFrInt_SHIFT (11) +#define S3C_DCFG_PerFrInt_LIMIT (0x3) +#define S3C_DCFG_PerFrInt(_x) ((_x) << 11) + +#define S3C_DCFG_DevAddr_MASK (0x7f << 4) +#define S3C_DCFG_DevAddr_SHIFT (4) +#define S3C_DCFG_DevAddr_LIMIT (0x7f) +#define S3C_DCFG_DevAddr(_x) ((_x) << 4) + +#define S3C_DCFG_NZStsOUTHShk (1 << 2) + +#define S3C_DCFG_DevSpd_MASK (0x3 << 0) +#define S3C_DCFG_DevSpd_SHIFT (0) +#define S3C_DCFG_DevSpd_HS (0x0 << 0) +#define S3C_DCFG_DevSpd_FS (0x1 << 0) +#define S3C_DCFG_DevSpd_LS (0x2 << 0) +#define S3C_DCFG_DevSpd_FS48 (0x3 << 0) + +#define S3C_DCTL S3C_HSOTG_REG(0x804) + +#define S3C_DCTL_PWROnPrgDone (1 << 11) +#define S3C_DCTL_CGOUTNak (1 << 10) +#define S3C_DCTL_SGOUTNak (1 << 9) +#define S3C_DCTL_CGNPInNAK (1 << 8) +#define S3C_DCTL_SGNPInNAK (1 << 7) +#define S3C_DCTL_TstCtl_MASK (0x7 << 4) +#define S3C_DCTL_TstCtl_SHIFT (4) +#define S3C_DCTL_GOUTNakSts (1 << 3) +#define S3C_DCTL_GNPINNakSts (1 << 2) +#define S3C_DCTL_SftDiscon (1 << 1) +#define S3C_DCTL_RmtWkUpSig (1 << 0) + +#define S3C_DSTS S3C_HSOTG_REG(0x808) + +#define S3C_DSTS_SOFFN_MASK (0x3fff << 8) +#define S3C_DSTS_SOFFN_SHIFT (8) +#define S3C_DSTS_SOFFN_LIMIT (0x3fff) +#define S3C_DSTS_SOFFN(_x) ((_x) << 8) +#define S3C_DSTS_ErraticErr (1 << 3) +#define S3C_DSTS_EnumSpd_MASK (0x3 << 1) +#define S3C_DSTS_EnumSpd_SHIFT (1) +#define S3C_DSTS_EnumSpd_HS (0x0 << 1) +#define S3C_DSTS_EnumSpd_FS (0x1 << 1) +#define S3C_DSTS_EnumSpd_LS (0x2 << 1) +#define S3C_DSTS_EnumSpd_FS48 (0x3 << 1) + +#define S3C_DSTS_SuspSts (1 << 0) + +#define S3C_DIEPMSK S3C_HSOTG_REG(0x810) + +#define S3C_DIEPMSK_TxFIFOEmpty (1 << 7) +#define S3C_DIEPMSK_INEPNakEffMsk (1 << 6) +#define S3C_DIEPMSK_INTknEPMisMsk (1 << 5) +#define S3C_DIEPMSK_INTknTXFEmpMsk (1 << 4) +#define S3C_DIEPMSK_TimeOUTMsk (1 << 3) +#define S3C_DIEPMSK_AHBErrMsk (1 << 2) +#define S3C_DIEPMSK_EPDisbldMsk (1 << 1) +#define S3C_DIEPMSK_XferComplMsk (1 << 0) + +#define S3C_DOEPMSK S3C_HSOTG_REG(0x814) + +#define S3C_DOEPMSK_Back2BackSetup (1 << 6) +#define S3C_DOEPMSK_OUTTknEPdisMsk (1 << 4) +#define S3C_DOEPMSK_SetupMsk (1 << 3) +#define S3C_DOEPMSK_AHBErrMsk (1 << 2) +#define S3C_DOEPMSK_EPDisbldMsk (1 << 1) +#define S3C_DOEPMSK_XferComplMsk (1 << 0) + +#define S3C_DAINT S3C_HSOTG_REG(0x818) +#define S3C_DAINTMSK S3C_HSOTG_REG(0x81C) + +#define S3C_DAINT_OutEP_SHIFT (16) +#define S3C_DAINT_OutEP(x) (1 << ((x) + 16)) +#define S3C_DAINT_InEP(x) (1 << (x)) + +#define S3C_DTKNQR1 S3C_HSOTG_REG(0x820) +#define S3C_DTKNQR2 S3C_HSOTG_REG(0x824) +#define S3C_DTKNQR3 S3C_HSOTG_REG(0x830) +#define S3C_DTKNQR4 S3C_HSOTG_REG(0x834) + +#define S3C_DVBUSDIS S3C_HSOTG_REG(0x828) +#define S3C_DVBUSPULSE S3C_HSOTG_REG(0x82C) + +#define S3C_DIEPCTL0 S3C_HSOTG_REG(0x900) +#define S3C_DOEPCTL0 S3C_HSOTG_REG(0xB00) +#define S3C_DIEPCTL(_a) S3C_HSOTG_REG(0x900 + ((_a) * 0x20)) +#define S3C_DOEPCTL(_a) S3C_HSOTG_REG(0xB00 + ((_a) * 0x20)) + +/* EP0 specialness: + * bits[29..28] - reserved (no SetD0PID, SetD1PID) + * bits[25..22] - should always be zero, this isn't a periodic endpoint + * bits[10..0] - MPS setting differenct for EP0 +*/ +#define S3C_D0EPCTL_MPS_MASK (0x3 << 0) +#define S3C_D0EPCTL_MPS_SHIFT (0) +#define S3C_D0EPCTL_MPS_64 (0x0 << 0) +#define S3C_D0EPCTL_MPS_32 (0x1 << 0) +#define S3C_D0EPCTL_MPS_16 (0x2 << 0) +#define S3C_D0EPCTL_MPS_8 (0x3 << 0) + +#define S3C_DxEPCTL_EPEna (1 << 31) +#define S3C_DxEPCTL_EPDis (1 << 30) +#define S3C_DxEPCTL_SetD1PID (1 << 29) +#define S3C_DxEPCTL_SetOddFr (1 << 29) +#define S3C_DxEPCTL_SetD0PID (1 << 28) +#define S3C_DxEPCTL_SetEvenFr (1 << 28) +#define S3C_DxEPCTL_SNAK (1 << 27) +#define S3C_DxEPCTL_CNAK (1 << 26) +#define S3C_DxEPCTL_TxFNum_MASK (0xf << 22) +#define S3C_DxEPCTL_TxFNum_SHIFT (22) +#define S3C_DxEPCTL_TxFNum_LIMIT (0xf) +#define S3C_DxEPCTL_TxFNum(_x) ((_x) << 22) + +#define S3C_DxEPCTL_Stall (1 << 21) +#define S3C_DxEPCTL_Snp (1 << 20) +#define S3C_DxEPCTL_EPType_MASK (0x3 << 18) +#define S3C_DxEPCTL_EPType_SHIFT (18) +#define S3C_DxEPCTL_EPType_Control (0x0 << 18) +#define S3C_DxEPCTL_EPType_Iso (0x1 << 18) +#define S3C_DxEPCTL_EPType_Bulk (0x2 << 18) +#define S3C_DxEPCTL_EPType_Intterupt (0x3 << 18) + +#define S3C_DxEPCTL_NAKsts (1 << 17) +#define S3C_DxEPCTL_DPID (1 << 16) +#define S3C_DxEPCTL_EOFrNum (1 << 16) +#define S3C_DxEPCTL_USBActEp (1 << 15) +#define S3C_DxEPCTL_NextEp_MASK (0xf << 11) +#define S3C_DxEPCTL_NextEp_SHIFT (11) +#define S3C_DxEPCTL_NextEp_LIMIT (0xf) +#define S3C_DxEPCTL_NextEp(_x) ((_x) << 11) + +#define S3C_DxEPCTL_MPS_MASK (0x7ff << 0) +#define S3C_DxEPCTL_MPS_SHIFT (0) +#define S3C_DxEPCTL_MPS_LIMIT (0x7ff) +#define S3C_DxEPCTL_MPS(_x) ((_x) << 0) + +#define S3C_DIEPINT(_a) S3C_HSOTG_REG(0x908 + ((_a) * 0x20)) +#define S3C_DOEPINT(_a) S3C_HSOTG_REG(0xB08 + ((_a) * 0x20)) + +#define S3C_DxEPINT_INEPNakEff (1 << 6) +#define S3C_DxEPINT_Back2BackSetup (1 << 6) +#define S3C_DxEPINT_INTknEPMis (1 << 5) +#define S3C_DxEPINT_INTknTXFEmp (1 << 4) +#define S3C_DxEPINT_OUTTknEPdis (1 << 4) +#define S3C_DxEPINT_Timeout (1 << 3) +#define S3C_DxEPINT_Setup (1 << 3) +#define S3C_DxEPINT_AHBErr (1 << 2) +#define S3C_DxEPINT_EPDisbld (1 << 1) +#define S3C_DxEPINT_XferCompl (1 << 0) + +#define S3C_DIEPTSIZ0 S3C_HSOTG_REG(0x910) + +#define S3C_DIEPTSIZ0_PktCnt_MASK (0x3 << 19) +#define S3C_DIEPTSIZ0_PktCnt_SHIFT (19) +#define S3C_DIEPTSIZ0_PktCnt_LIMIT (0x3) +#define S3C_DIEPTSIZ0_PktCnt(_x) ((_x) << 19) + +#define S3C_DIEPTSIZ0_XferSize_MASK (0x7f << 0) +#define S3C_DIEPTSIZ0_XferSize_SHIFT (0) +#define S3C_DIEPTSIZ0_XferSize_LIMIT (0x7f) +#define S3C_DIEPTSIZ0_XferSize(_x) ((_x) << 0) + + +#define DOEPTSIZ0 S3C_HSOTG_REG(0xB10) +#define S3C_DOEPTSIZ0_SUPCnt_MASK (0x3 << 29) +#define S3C_DOEPTSIZ0_SUPCnt_SHIFT (29) +#define S3C_DOEPTSIZ0_SUPCnt_LIMIT (0x3) +#define S3C_DOEPTSIZ0_SUPCnt(_x) ((_x) << 29) + +#define S3C_DOEPTSIZ0_PktCnt (1 << 19) +#define S3C_DOEPTSIZ0_XferSize_MASK (0x7f << 0) +#define S3C_DOEPTSIZ0_XferSize_SHIFT (0) + +#define S3C_DIEPTSIZ(_a) S3C_HSOTG_REG(0x910 + ((_a) * 0x20)) +#define S3C_DOEPTSIZ(_a) S3C_HSOTG_REG(0xB10 + ((_a) * 0x20)) + +#define S3C_DxEPTSIZ_MC_MASK (0x3 << 29) +#define S3C_DxEPTSIZ_MC_SHIFT (29) +#define S3C_DxEPTSIZ_MC_LIMIT (0x3) +#define S3C_DxEPTSIZ_MC(_x) ((_x) << 29) + +#define S3C_DxEPTSIZ_PktCnt_MASK (0x3ff << 19) +#define S3C_DxEPTSIZ_PktCnt_SHIFT (19) +#define S3C_DxEPTSIZ_PktCnt_GET(_v) (((_v) >> 19) & 0x3ff) +#define S3C_DxEPTSIZ_PktCnt_LIMIT (0x3ff) +#define S3C_DxEPTSIZ_PktCnt(_x) ((_x) << 19) + +#define S3C_DxEPTSIZ_XferSize_MASK (0x7ffff << 0) +#define S3C_DxEPTSIZ_XferSize_SHIFT (0) +#define S3C_DxEPTSIZ_XferSize_GET(_v) (((_v) >> 0) & 0x7ffff) +#define S3C_DxEPTSIZ_XferSize_LIMIT (0x7ffff) +#define S3C_DxEPTSIZ_XferSize(_x) ((_x) << 0) + + +#define S3C_DIEPDMA(_a) S3C_HSOTG_REG(0x914 + ((_a) * 0x20)) +#define S3C_DOEPDMA(_a) S3C_HSOTG_REG(0xB14 + ((_a) * 0x20)) +#define S3C_DTXFSTS(_a) S3C_HSOTG_REG(0x918 + ((_a) * 0x20)) + +#define S3C_EPFIFO(_a) S3C_HSOTG_REG(0x1000 + ((_a) * 0x1000)) + +#endif /* __PLAT_S3C64XX_REGS_USB_HSOTG_H */ diff --git a/include/linux/platform_data/s3c-hsotg.h b/include/linux/platform_data/s3c-hsotg.h new file mode 100644 index 000000000000..97ec12c2ded4 --- /dev/null +++ b/include/linux/platform_data/s3c-hsotg.h @@ -0,0 +1,35 @@ +/* include/linux/platform_data/s3c-hsotg.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks + * http://armlinux.simtec.co.uk/ + * + * S3C USB2.0 High-speed / OtG platform information + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +enum s3c_hsotg_dmamode { + S3C_HSOTG_DMA_NONE, /* do not use DMA at-all */ + S3C_HSOTG_DMA_ONLY, /* always use DMA */ + S3C_HSOTG_DMA_DRV, /* DMA is chosen by driver */ +}; + +/** + * struct s3c_hsotg_plat - platform data for high-speed otg/udc + * @dma: Whether to use DMA or not. + * @is_osc: The clock source is an oscillator, not a crystal + */ +struct s3c_hsotg_plat { + enum s3c_hsotg_dmamode dma; + unsigned int is_osc:1; + int phy_type; + + int (*phy_init)(struct platform_device *pdev, int type); + int (*phy_exit)(struct platform_device *pdev, int type); +}; + +extern void s3c_hsotg_set_platdata(struct s3c_hsotg_plat *pd); -- cgit v1.2.3 From aaeb6dfff02f9c1077c2a09c45b99f6255ef9159 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Fri, 11 May 2012 15:35:32 +0200 Subject: ARM: AT91: Add platform data for the AT91 ADCs The AT91 SoCs often embeds an ADC. This patch adds the needed platform data to specify the informations required by the driver to work properly. For now, we only need the reference voltage and which channels are available on the board. Signed-off-by: Maxime Ripard Acked-by: Nicolas Ferre Acked-by: Jonathan Cameron Signed-off-by: Greg Kroah-Hartman --- include/linux/platform_data/at91_adc.h | 61 ++++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 include/linux/platform_data/at91_adc.h (limited to 'include/linux/platform_data') diff --git a/include/linux/platform_data/at91_adc.h b/include/linux/platform_data/at91_adc.h new file mode 100644 index 000000000000..e15745b4f3a5 --- /dev/null +++ b/include/linux/platform_data/at91_adc.h @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2011 Free Electrons + * + * Licensed under the GPLv2 or later. + */ + +#ifndef _AT91_ADC_H_ +#define _AT91_ADC_H_ + +/** + * struct at91_adc_reg_desc - Various informations relative to registers + * @channel_base: Base offset for the channel data registers + * @drdy_mask: Mask of the DRDY field in the relevant registers + (Interruptions registers mostly) + * @status_register: Offset of the Interrupt Status Register + * @trigger_register: Offset of the Trigger setup register + */ +struct at91_adc_reg_desc { + u8 channel_base; + u32 drdy_mask; + u8 status_register; + u8 trigger_register; +}; + +/** + * struct at91_adc_trigger - description of triggers + * @name: name of the trigger advertised to the user + * @value: value to set in the ADC's trigger setup register + to enable the trigger + * @is_external: Does the trigger rely on an external pin? + */ +struct at91_adc_trigger { + const char *name; + u8 value; + bool is_external; +}; + +/** + * struct at91_adc_data - platform data for ADC driver + * @channels_used: channels in use on the board as a bitmask + * @num_channels: global number of channels available on the board + * @registers: Registers definition on the board + * @startup_time: startup time of the ADC in microseconds + * @trigger_list: Triggers available in the ADC + * @trigger_number: Number of triggers available in the ADC + * @use_external_triggers: does the board has external triggers availables + * @vref: Reference voltage for the ADC in millivolts + */ +struct at91_adc_data { + unsigned long channels_used; + u8 num_channels; + struct at91_adc_reg_desc *registers; + u8 startup_time; + struct at91_adc_trigger *trigger_list; + u8 trigger_number; + bool use_external_triggers; + u16 vref; +}; + +extern void __init at91_add_device_adc(struct at91_adc_data *data); +#endif -- cgit v1.2.3 From a07e103ef08c6907d695a06467d7ee950796fccf Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Thu, 17 May 2012 15:22:23 +0900 Subject: gpio: Emma Mobile GPIO driver V2 This patch is V2 of the Emma Mobile GPIO driver. This driver is designed to be reusable between multiple SoCs that share the same basic building block, but so far it has only been used on Emma Mobile EV2. Each driver instance handles 32 GPIOs with individually maskable IRQs. The driver operates on two I/O memory ranges and the 32 GPIOs are hooked up to two interrupts. In the case of Emma Mobile EV2 this GPIO building block is used as main external interrupt controller hooking up 159 GPIOS as 159 interrupts via 5 driver instances and 10 interrupts to the GIC and the Cortex-A9 Dual. Signed-off-by: Magnus Damm Acked-by: Linus Walleij Signed-off-by: Rafael J. Wysocki --- drivers/gpio/Kconfig | 6 + drivers/gpio/Makefile | 1 + drivers/gpio/gpio-em.c | 418 ++++++++++++++++++++++++++++++++++ include/linux/platform_data/gpio-em.h | 10 + 4 files changed, 435 insertions(+) create mode 100644 drivers/gpio/gpio-em.c create mode 100644 include/linux/platform_data/gpio-em.h (limited to 'include/linux/platform_data') diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index e03653d69357..eb80ba300452 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -91,6 +91,12 @@ config GPIO_IT8761E help Say yes here to support GPIO functionality of IT8761E super I/O chip. +config GPIO_EM + tristate "Emma Mobile GPIO" + depends on ARM + help + Say yes here to support GPIO on Renesas Emma Mobile SoCs. + config GPIO_EP93XX def_bool y depends on ARCH_EP93XX diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 007f54bd0081..3f1f829260bb 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_GPIO_BT8XX) += gpio-bt8xx.o obj-$(CONFIG_GPIO_CS5535) += gpio-cs5535.o obj-$(CONFIG_GPIO_DA9052) += gpio-da9052.o obj-$(CONFIG_ARCH_DAVINCI) += gpio-davinci.o +obj-$(CONFIG_GPIO_EM) += gpio-em.o obj-$(CONFIG_GPIO_EP93XX) += gpio-ep93xx.o obj-$(CONFIG_GPIO_GE_FPGA) += gpio-ge.o obj-$(CONFIG_GPIO_IT8761E) += gpio-it8761e.o diff --git a/drivers/gpio/gpio-em.c b/drivers/gpio/gpio-em.c new file mode 100644 index 000000000000..150d9768811d --- /dev/null +++ b/drivers/gpio/gpio-em.c @@ -0,0 +1,418 @@ +/* + * Emma Mobile GPIO Support - GIO + * + * Copyright (C) 2012 Magnus Damm + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct em_gio_priv { + void __iomem *base0; + void __iomem *base1; + unsigned int irq_base; + spinlock_t sense_lock; + struct platform_device *pdev; + struct gpio_chip gpio_chip; + struct irq_chip irq_chip; + struct irq_domain *irq_domain; +}; + +#define GIO_E1 0x00 +#define GIO_E0 0x04 +#define GIO_EM 0x04 +#define GIO_OL 0x08 +#define GIO_OH 0x0c +#define GIO_I 0x10 +#define GIO_IIA 0x14 +#define GIO_IEN 0x18 +#define GIO_IDS 0x1c +#define GIO_IIM 0x1c +#define GIO_RAW 0x20 +#define GIO_MST 0x24 +#define GIO_IIR 0x28 + +#define GIO_IDT0 0x40 +#define GIO_IDT1 0x44 +#define GIO_IDT2 0x48 +#define GIO_IDT3 0x4c +#define GIO_RAWBL 0x50 +#define GIO_RAWBH 0x54 +#define GIO_IRBL 0x58 +#define GIO_IRBH 0x5c + +#define GIO_IDT(n) (GIO_IDT0 + ((n) * 4)) + +static inline unsigned long em_gio_read(struct em_gio_priv *p, int offs) +{ + if (offs < GIO_IDT0) + return ioread32(p->base0 + offs); + else + return ioread32(p->base1 + (offs - GIO_IDT0)); +} + +static inline void em_gio_write(struct em_gio_priv *p, int offs, + unsigned long value) +{ + if (offs < GIO_IDT0) + iowrite32(value, p->base0 + offs); + else + iowrite32(value, p->base1 + (offs - GIO_IDT0)); +} + +static inline struct em_gio_priv *irq_to_priv(struct irq_data *d) +{ + struct irq_chip *chip = irq_data_get_irq_chip(d); + return container_of(chip, struct em_gio_priv, irq_chip); +} + +static void em_gio_irq_disable(struct irq_data *d) +{ + struct em_gio_priv *p = irq_to_priv(d); + + em_gio_write(p, GIO_IDS, BIT(irqd_to_hwirq(d))); +} + +static void em_gio_irq_enable(struct irq_data *d) +{ + struct em_gio_priv *p = irq_to_priv(d); + + em_gio_write(p, GIO_IEN, BIT(irqd_to_hwirq(d))); +} + +#define GIO_ASYNC(x) (x + 8) + +static unsigned char em_gio_sense_table[IRQ_TYPE_SENSE_MASK + 1] = { + [IRQ_TYPE_EDGE_RISING] = GIO_ASYNC(0x00), + [IRQ_TYPE_EDGE_FALLING] = GIO_ASYNC(0x01), + [IRQ_TYPE_LEVEL_HIGH] = GIO_ASYNC(0x02), + [IRQ_TYPE_LEVEL_LOW] = GIO_ASYNC(0x03), + [IRQ_TYPE_EDGE_BOTH] = GIO_ASYNC(0x04), +}; + +static int em_gio_irq_set_type(struct irq_data *d, unsigned int type) +{ + unsigned char value = em_gio_sense_table[type & IRQ_TYPE_SENSE_MASK]; + struct em_gio_priv *p = irq_to_priv(d); + unsigned int reg, offset, shift; + unsigned long flags; + unsigned long tmp; + + if (!value) + return -EINVAL; + + offset = irqd_to_hwirq(d); + + pr_debug("gio: sense irq = %d, mode = %d\n", offset, value); + + /* 8 x 4 bit fields in 4 IDT registers */ + reg = GIO_IDT(offset >> 3); + shift = (offset & 0x07) << 4; + + spin_lock_irqsave(&p->sense_lock, flags); + + /* disable the interrupt in IIA */ + tmp = em_gio_read(p, GIO_IIA); + tmp &= ~BIT(offset); + em_gio_write(p, GIO_IIA, tmp); + + /* change the sense setting in IDT */ + tmp = em_gio_read(p, reg); + tmp &= ~(0xf << shift); + tmp |= value << shift; + em_gio_write(p, reg, tmp); + + /* clear pending interrupts */ + em_gio_write(p, GIO_IIR, BIT(offset)); + + /* enable the interrupt in IIA */ + tmp = em_gio_read(p, GIO_IIA); + tmp |= BIT(offset); + em_gio_write(p, GIO_IIA, tmp); + + spin_unlock_irqrestore(&p->sense_lock, flags); + + return 0; +} + +static irqreturn_t em_gio_irq_handler(int irq, void *dev_id) +{ + struct em_gio_priv *p = dev_id; + unsigned long pending; + unsigned int offset, irqs_handled = 0; + + while ((pending = em_gio_read(p, GIO_MST))) { + offset = __ffs(pending); + em_gio_write(p, GIO_IIR, BIT(offset)); + generic_handle_irq(irq_find_mapping(p->irq_domain, offset)); + irqs_handled++; + } + + return irqs_handled ? IRQ_HANDLED : IRQ_NONE; +} + +static inline struct em_gio_priv *gpio_to_priv(struct gpio_chip *chip) +{ + return container_of(chip, struct em_gio_priv, gpio_chip); +} + +static int em_gio_direction_input(struct gpio_chip *chip, unsigned offset) +{ + em_gio_write(gpio_to_priv(chip), GIO_E0, BIT(offset)); + return 0; +} + +static int em_gio_get(struct gpio_chip *chip, unsigned offset) +{ + return (int)(em_gio_read(gpio_to_priv(chip), GIO_I) & BIT(offset)); +} + +static void __em_gio_set(struct gpio_chip *chip, unsigned int reg, + unsigned shift, int value) +{ + /* upper 16 bits contains mask and lower 16 actual value */ + em_gio_write(gpio_to_priv(chip), reg, + (1 << (shift + 16)) | (value << shift)); +} + +static void em_gio_set(struct gpio_chip *chip, unsigned offset, int value) +{ + /* output is split into two registers */ + if (offset < 16) + __em_gio_set(chip, GIO_OL, offset, value); + else + __em_gio_set(chip, GIO_OH, offset - 16, value); +} + +static int em_gio_direction_output(struct gpio_chip *chip, unsigned offset, + int value) +{ + /* write GPIO value to output before selecting output mode of pin */ + em_gio_set(chip, offset, value); + em_gio_write(gpio_to_priv(chip), GIO_E1, BIT(offset)); + return 0; +} + +static int em_gio_to_irq(struct gpio_chip *chip, unsigned offset) +{ + return irq_find_mapping(gpio_to_priv(chip)->irq_domain, offset); +} + +static int em_gio_irq_domain_map(struct irq_domain *h, unsigned int virq, + irq_hw_number_t hw) +{ + struct em_gio_priv *p = h->host_data; + + pr_debug("gio: map hw irq = %d, virq = %d\n", (int)hw, virq); + + irq_set_chip_data(virq, h->host_data); + irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq); + set_irq_flags(virq, IRQF_VALID); /* kill me now */ + return 0; +} + +static struct irq_domain_ops em_gio_irq_domain_ops = { + .map = em_gio_irq_domain_map, +}; + +static int __devinit em_gio_irq_domain_init(struct em_gio_priv *p) +{ + struct platform_device *pdev = p->pdev; + struct gpio_em_config *pdata = pdev->dev.platform_data; + + p->irq_base = irq_alloc_descs(pdata->irq_base, 0, + pdata->number_of_pins, numa_node_id()); + if (IS_ERR_VALUE(p->irq_base)) { + dev_err(&pdev->dev, "cannot get irq_desc\n"); + return -ENXIO; + } + pr_debug("gio: hw base = %d, nr = %d, sw base = %d\n", + pdata->gpio_base, pdata->number_of_pins, p->irq_base); + + p->irq_domain = irq_domain_add_legacy(pdev->dev.of_node, + pdata->number_of_pins, + p->irq_base, 0, + &em_gio_irq_domain_ops, p); + if (!p->irq_domain) { + irq_free_descs(p->irq_base, pdata->number_of_pins); + return -ENXIO; + } + + return 0; +} + +static void __devexit em_gio_irq_domain_cleanup(struct em_gio_priv *p) +{ + struct gpio_em_config *pdata = p->pdev->dev.platform_data; + + irq_free_descs(p->irq_base, pdata->number_of_pins); + /* FIXME: irq domain wants to be freed! */ +} + +static int __devinit em_gio_probe(struct platform_device *pdev) +{ + struct gpio_em_config *pdata = pdev->dev.platform_data; + struct em_gio_priv *p; + struct resource *io[2], *irq[2]; + struct gpio_chip *gpio_chip; + struct irq_chip *irq_chip; + const char *name = dev_name(&pdev->dev); + int ret; + + p = kzalloc(sizeof(*p), GFP_KERNEL); + if (!p) { + dev_err(&pdev->dev, "failed to allocate driver data\n"); + ret = -ENOMEM; + goto err0; + } + + p->pdev = pdev; + platform_set_drvdata(pdev, p); + spin_lock_init(&p->sense_lock); + + io[0] = platform_get_resource(pdev, IORESOURCE_MEM, 0); + io[1] = platform_get_resource(pdev, IORESOURCE_MEM, 1); + irq[0] = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + irq[1] = platform_get_resource(pdev, IORESOURCE_IRQ, 1); + + if (!io[0] || !io[1] || !irq[0] || !irq[1] || !pdata) { + dev_err(&pdev->dev, "missing IRQ, IOMEM or configuration\n"); + ret = -EINVAL; + goto err1; + } + + p->base0 = ioremap_nocache(io[0]->start, resource_size(io[0])); + if (!p->base0) { + dev_err(&pdev->dev, "failed to remap low I/O memory\n"); + ret = -ENXIO; + goto err1; + } + + p->base1 = ioremap_nocache(io[1]->start, resource_size(io[1])); + if (!p->base1) { + dev_err(&pdev->dev, "failed to remap high I/O memory\n"); + ret = -ENXIO; + goto err2; + } + + gpio_chip = &p->gpio_chip; + gpio_chip->direction_input = em_gio_direction_input; + gpio_chip->get = em_gio_get; + gpio_chip->direction_output = em_gio_direction_output; + gpio_chip->set = em_gio_set; + gpio_chip->to_irq = em_gio_to_irq; + gpio_chip->label = name; + gpio_chip->owner = THIS_MODULE; + gpio_chip->base = pdata->gpio_base; + gpio_chip->ngpio = pdata->number_of_pins; + + irq_chip = &p->irq_chip; + irq_chip->name = name; + irq_chip->irq_mask = em_gio_irq_disable; + irq_chip->irq_unmask = em_gio_irq_enable; + irq_chip->irq_enable = em_gio_irq_enable; + irq_chip->irq_disable = em_gio_irq_disable; + irq_chip->irq_set_type = em_gio_irq_set_type; + irq_chip->flags = IRQCHIP_SKIP_SET_WAKE; + + ret = em_gio_irq_domain_init(p); + if (ret) { + dev_err(&pdev->dev, "cannot initialize irq domain\n"); + goto err3; + } + + if (request_irq(irq[0]->start, em_gio_irq_handler, 0, name, p)) { + dev_err(&pdev->dev, "failed to request low IRQ\n"); + ret = -ENOENT; + goto err4; + } + + if (request_irq(irq[1]->start, em_gio_irq_handler, 0, name, p)) { + dev_err(&pdev->dev, "failed to request high IRQ\n"); + ret = -ENOENT; + goto err5; + } + + ret = gpiochip_add(gpio_chip); + if (ret) { + dev_err(&pdev->dev, "failed to add GPIO controller\n"); + goto err6; + } + return 0; + +err6: + free_irq(irq[1]->start, pdev); +err5: + free_irq(irq[0]->start, pdev); +err4: + em_gio_irq_domain_cleanup(p); +err3: + iounmap(p->base1); +err2: + iounmap(p->base0); +err1: + kfree(p); +err0: + return ret; +} + +static int __devexit em_gio_remove(struct platform_device *pdev) +{ + struct em_gio_priv *p = platform_get_drvdata(pdev); + struct resource *irq[2]; + int ret; + + ret = gpiochip_remove(&p->gpio_chip); + if (ret) + return ret; + + irq[0] = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + irq[1] = platform_get_resource(pdev, IORESOURCE_IRQ, 1); + + free_irq(irq[1]->start, pdev); + free_irq(irq[0]->start, pdev); + em_gio_irq_domain_cleanup(p); + iounmap(p->base1); + iounmap(p->base0); + kfree(p); + return 0; +} + +static struct platform_driver em_gio_device_driver = { + .probe = em_gio_probe, + .remove = __devexit_p(em_gio_remove), + .driver = { + .name = "em_gio", + } +}; + +module_platform_driver(em_gio_device_driver); + +MODULE_AUTHOR("Magnus Damm"); +MODULE_DESCRIPTION("Renesas Emma Mobile GIO Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/include/linux/platform_data/gpio-em.h b/include/linux/platform_data/gpio-em.h new file mode 100644 index 000000000000..573edfb046c4 --- /dev/null +++ b/include/linux/platform_data/gpio-em.h @@ -0,0 +1,10 @@ +#ifndef __GPIO_EM_H__ +#define __GPIO_EM_H__ + +struct gpio_em_config { + unsigned int gpio_base; + unsigned int irq_base; + unsigned int number_of_pins; +}; + +#endif /* __GPIO_EM_H__ */ -- cgit v1.2.3 From f7c2fe386ae92b471a0edd4fa4bed7033224b9bf Mon Sep 17 00:00:00 2001 From: "Felten, Lothar" Date: Sat, 12 May 2012 04:36:38 -0400 Subject: hwmon: INA219 and INA226 support Add support for the Texas Instruments INA219 and INA226 power monitors. Signed-off-by: Lothar Felten [guenter.roeck@ericsson.com: formatting cleanup; check for smbus word data; select PGA=8 for INA219] Signed-off-by: Guenter Roeck --- Documentation/hwmon/ina2xx | 29 +++ drivers/hwmon/Kconfig | 13 ++ drivers/hwmon/Makefile | 1 + drivers/hwmon/ina2xx.c | 368 +++++++++++++++++++++++++++++++++++ include/linux/platform_data/ina2xx.h | 19 ++ 5 files changed, 430 insertions(+) create mode 100644 Documentation/hwmon/ina2xx create mode 100644 drivers/hwmon/ina2xx.c create mode 100644 include/linux/platform_data/ina2xx.h (limited to 'include/linux/platform_data') diff --git a/Documentation/hwmon/ina2xx b/Documentation/hwmon/ina2xx new file mode 100644 index 000000000000..f50a6cc27616 --- /dev/null +++ b/Documentation/hwmon/ina2xx @@ -0,0 +1,29 @@ +Kernel driver ina2xx +==================== + +Supported chips: + * Texas Instruments INA219 + Prefix: 'ina219' + Addresses: I2C 0x40 - 0x4f + Datasheet: Publicly available at the Texas Instruments website + http://www.ti.com/ + + * Texas Instruments INA226 + Prefix: 'ina226' + Addresses: I2C 0x40 - 0x4f + Datasheet: Publicly available at the Texas Instruments website + http://www.ti.com/ + +Author: Lothar Felten + +Description +----------- + +The INA219 is a high-side current shunt and power monitor with an I2C +interface. The INA219 monitors both shunt drop and supply voltage, with +programmable conversion times and filtering. + +The INA226 is a current shunt and power monitor with an I2C interface. +The INA226 monitors both a shunt voltage drop and bus supply voltage. + +The shunt value in micro-ohms can be set via platform data. diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig index 8deedc1b9840..1c7bbd458902 100644 --- a/drivers/hwmon/Kconfig +++ b/drivers/hwmon/Kconfig @@ -1102,6 +1102,19 @@ config SENSORS_AMC6821 This driver can also be build as a module. If so, the module will be called amc6821. +config SENSORS_INA2XX + tristate "Texas Instruments INA219, INA226" + depends on I2C && EXPERIMENTAL + help + If you say yes here you get support for INA219 and INA226 power + monitor chips. + + The INA2xx driver is configured for the default configuration of + the part as described in the datasheet. + Default value for Rshunt is 10 mOhms. + This driver can also be built as a module. If so, the module + will be called ina2xx. + config SENSORS_THMC50 tristate "Texas Instruments THMC50 / Analog Devices ADM1022" depends on I2C diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile index 6d3f11f71815..e1eeac13b851 100644 --- a/drivers/hwmon/Makefile +++ b/drivers/hwmon/Makefile @@ -62,6 +62,7 @@ obj-$(CONFIG_SENSORS_ULTRA45) += ultra45_env.o obj-$(CONFIG_SENSORS_I5K_AMB) += i5k_amb.o obj-$(CONFIG_SENSORS_IBMAEM) += ibmaem.o obj-$(CONFIG_SENSORS_IBMPEX) += ibmpex.o +obj-$(CONFIG_SENSORS_INA2XX) += ina2xx.o obj-$(CONFIG_SENSORS_IT87) += it87.o obj-$(CONFIG_SENSORS_JC42) += jc42.o obj-$(CONFIG_SENSORS_JZ4740) += jz4740-hwmon.o diff --git a/drivers/hwmon/ina2xx.c b/drivers/hwmon/ina2xx.c new file mode 100644 index 000000000000..7f3f4a385729 --- /dev/null +++ b/drivers/hwmon/ina2xx.c @@ -0,0 +1,368 @@ +/* + * Driver for Texas Instruments INA219, INA226 power monitor chips + * + * INA219: + * Zero Drift Bi-Directional Current/Power Monitor with I2C Interface + * Datasheet: http://www.ti.com/product/ina219 + * + * INA226: + * Bi-Directional Current/Power Monitor with I2C Interface + * Datasheet: http://www.ti.com/product/ina226 + * + * Copyright (C) 2012 Lothar Felten + * Thanks to Jan Volkering + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +/* common register definitions */ +#define INA2XX_CONFIG 0x00 +#define INA2XX_SHUNT_VOLTAGE 0x01 /* readonly */ +#define INA2XX_BUS_VOLTAGE 0x02 /* readonly */ +#define INA2XX_POWER 0x03 /* readonly */ +#define INA2XX_CURRENT 0x04 /* readonly */ +#define INA2XX_CALIBRATION 0x05 + +/* INA226 register definitions */ +#define INA226_MASK_ENABLE 0x06 +#define INA226_ALERT_LIMIT 0x07 +#define INA226_DIE_ID 0xFF + + +/* register count */ +#define INA219_REGISTERS 6 +#define INA226_REGISTERS 8 + +#define INA2XX_MAX_REGISTERS 8 + +/* settings - depend on use case */ +#define INA219_CONFIG_DEFAULT 0x399F /* PGA=8 */ +#define INA226_CONFIG_DEFAULT 0x4527 /* averages=16 */ + +/* worst case is 68.10 ms (~14.6Hz, ina219) */ +#define INA2XX_CONVERSION_RATE 15 + +enum ina2xx_ids { ina219, ina226 }; + +struct ina2xx_data { + struct device *hwmon_dev; + + struct mutex update_lock; + bool valid; + unsigned long last_updated; + + int kind; + int registers; + u16 regs[INA2XX_MAX_REGISTERS]; +}; + +int ina2xx_read_word(struct i2c_client *client, int reg) +{ + int val = i2c_smbus_read_word_data(client, reg); + if (unlikely(val < 0)) { + dev_dbg(&client->dev, + "Failed to read register: %d\n", reg); + return val; + } + return be16_to_cpu(val); +} + +void ina2xx_write_word(struct i2c_client *client, int reg, int data) +{ + i2c_smbus_write_word_data(client, reg, cpu_to_be16(data)); +} + +static struct ina2xx_data *ina2xx_update_device(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct ina2xx_data *data = i2c_get_clientdata(client); + struct ina2xx_data *ret = data; + + mutex_lock(&data->update_lock); + + if (time_after(jiffies, data->last_updated + + HZ / INA2XX_CONVERSION_RATE) || !data->valid) { + + int i; + + dev_dbg(&client->dev, "Starting ina2xx update\n"); + + /* Read all registers */ + for (i = 0; i < data->registers; i++) { + int rv = ina2xx_read_word(client, i); + if (rv < 0) { + ret = ERR_PTR(rv); + goto abort; + } + data->regs[i] = rv; + } + data->last_updated = jiffies; + data->valid = 1; + } +abort: + mutex_unlock(&data->update_lock); + return ret; +} + +static int ina219_get_value(struct ina2xx_data *data, u8 reg) +{ + /* + * calculate exact value for the given register + * we assume default power-on reset settings: + * bus voltage range 32V + * gain = /8 + * adc 1 & 2 -> conversion time 532uS + * mode is continuous shunt and bus + * calibration value is INA219_CALIBRATION_VALUE + */ + int val = data->regs[reg]; + + switch (reg) { + case INA2XX_SHUNT_VOLTAGE: + /* LSB=10uV. Convert to mV. */ + val = DIV_ROUND_CLOSEST(val, 100); + break; + case INA2XX_BUS_VOLTAGE: + /* LSB=4mV. Register is not right aligned, convert to mV. */ + val = (val >> 3) * 4; + break; + case INA2XX_POWER: + /* LSB=20mW. Convert to uW */ + val = val * 20 * 1000; + break; + case INA2XX_CURRENT: + /* LSB=1mA (selected). Is in mA */ + break; + default: + /* programmer goofed */ + WARN_ON_ONCE(1); + val = 0; + break; + } + + return val; +} + +static int ina226_get_value(struct ina2xx_data *data, u8 reg) +{ + /* + * calculate exact value for the given register + * we assume default power-on reset settings: + * bus voltage range 32V + * gain = /8 + * adc 1 & 2 -> conversion time 532uS + * mode is continuous shunt and bus + * calibration value is INA226_CALIBRATION_VALUE + */ + int val = data->regs[reg]; + + switch (reg) { + case INA2XX_SHUNT_VOLTAGE: + /* LSB=2.5uV. Convert to mV. */ + val = DIV_ROUND_CLOSEST(val, 400); + break; + case INA2XX_BUS_VOLTAGE: + /* LSB=1.25mV. Convert to mV. */ + val = val + DIV_ROUND_CLOSEST(val, 4); + break; + case INA2XX_POWER: + /* LSB=25mW. Convert to uW */ + val = val * 25 * 1000; + break; + case INA2XX_CURRENT: + /* LSB=1mA (selected). Is in mA */ + break; + default: + /* programmer goofed */ + WARN_ON_ONCE(1); + val = 0; + break; + } + + return val; +} + +static ssize_t ina2xx_show_value(struct device *dev, + struct device_attribute *da, char *buf) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(da); + struct ina2xx_data *data = ina2xx_update_device(dev); + int value = 0; + + if (IS_ERR(data)) + return PTR_ERR(data); + + switch (data->kind) { + case ina219: + value = ina219_get_value(data, attr->index); + break; + case ina226: + value = ina226_get_value(data, attr->index); + break; + default: + WARN_ON_ONCE(1); + break; + } + return snprintf(buf, PAGE_SIZE, "%d\n", value); +} + +/* shunt voltage */ +static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, \ + ina2xx_show_value, NULL, INA2XX_SHUNT_VOLTAGE); + +/* bus voltage */ +static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, \ + ina2xx_show_value, NULL, INA2XX_BUS_VOLTAGE); + +/* calculated current */ +static SENSOR_DEVICE_ATTR(curr1_input, S_IRUGO, \ + ina2xx_show_value, NULL, INA2XX_CURRENT); + +/* calculated power */ +static SENSOR_DEVICE_ATTR(power1_input, S_IRUGO, \ + ina2xx_show_value, NULL, INA2XX_POWER); + +/* pointers to created device attributes */ +static struct attribute *ina2xx_attributes[] = { + &sensor_dev_attr_in0_input.dev_attr.attr, + &sensor_dev_attr_in1_input.dev_attr.attr, + &sensor_dev_attr_curr1_input.dev_attr.attr, + &sensor_dev_attr_power1_input.dev_attr.attr, + NULL, +}; + +static const struct attribute_group ina2xx_group = { + .attrs = ina2xx_attributes, +}; + +static int ina2xx_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct i2c_adapter *adapter = client->adapter; + struct ina2xx_data *data; + struct ina2xx_platform_data *pdata; + int ret = 0; + long shunt = 10000; /* default shunt value 10mOhms */ + + if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_WORD_DATA)) + return -ENODEV; + + data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + if (client->dev.platform_data) { + pdata = + (struct ina2xx_platform_data *)client->dev.platform_data; + shunt = pdata->shunt_uohms; + } + + if (shunt <= 0) + return -ENODEV; + + /* set the device type */ + data->kind = id->driver_data; + + switch (data->kind) { + case ina219: + /* device configuration */ + ina2xx_write_word(client, INA2XX_CONFIG, INA219_CONFIG_DEFAULT); + + /* set current LSB to 1mA, shunt is in uOhms */ + /* (equation 13 in datasheet) */ + ina2xx_write_word(client, INA2XX_CALIBRATION, 40960000 / shunt); + dev_info(&client->dev, + "power monitor INA219 (Rshunt = %li uOhm)\n", shunt); + data->registers = INA219_REGISTERS; + break; + case ina226: + /* device configuration */ + ina2xx_write_word(client, INA2XX_CONFIG, INA226_CONFIG_DEFAULT); + + /* set current LSB to 1mA, shunt is in uOhms */ + /* (equation 1 in datasheet)*/ + ina2xx_write_word(client, INA2XX_CALIBRATION, 5120000 / shunt); + dev_info(&client->dev, + "power monitor INA226 (Rshunt = %li uOhm)\n", shunt); + data->registers = INA226_REGISTERS; + break; + default: + /* unknown device id */ + return -ENODEV; + } + + i2c_set_clientdata(client, data); + mutex_init(&data->update_lock); + + ret = sysfs_create_group(&client->dev.kobj, &ina2xx_group); + if (ret) + return ret; + + data->hwmon_dev = hwmon_device_register(&client->dev); + if (IS_ERR(data->hwmon_dev)) { + ret = PTR_ERR(data->hwmon_dev); + goto out_err_hwmon; + } + + return 0; + +out_err_hwmon: + sysfs_remove_group(&client->dev.kobj, &ina2xx_group); + return ret; +} + +static int ina2xx_remove(struct i2c_client *client) +{ + struct ina2xx_data *data = i2c_get_clientdata(client); + + hwmon_device_unregister(data->hwmon_dev); + sysfs_remove_group(&client->dev.kobj, &ina2xx_group); + + return 0; +} + +static const struct i2c_device_id ina2xx_id[] = { + { "ina219", ina219 }, + { "ina226", ina226 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, ina2xx_id); + +static struct i2c_driver ina2xx_driver = { + .driver = { + .name = "ina2xx", + }, + .probe = ina2xx_probe, + .remove = ina2xx_remove, + .id_table = ina2xx_id, +}; + +static int __init ina2xx_init(void) +{ + return i2c_add_driver(&ina2xx_driver); +} + +static void __exit ina2xx_exit(void) +{ + i2c_del_driver(&ina2xx_driver); +} + +MODULE_AUTHOR("Lothar Felten "); +MODULE_DESCRIPTION("ina2xx driver"); +MODULE_LICENSE("GPL"); + +module_init(ina2xx_init); +module_exit(ina2xx_exit); diff --git a/include/linux/platform_data/ina2xx.h b/include/linux/platform_data/ina2xx.h new file mode 100644 index 000000000000..9abc0ca7259b --- /dev/null +++ b/include/linux/platform_data/ina2xx.h @@ -0,0 +1,19 @@ +/* + * Driver for Texas Instruments INA219, INA226 power monitor chips + * + * Copyright (C) 2012 Lothar Felten + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * For further information, see the Documentation/hwmon/ina2xx file. + */ + +/** + * struct ina2xx_platform_data - ina2xx info + * @shunt_uohms shunt resistance in microohms + */ +struct ina2xx_platform_data { + long shunt_uohms; +}; 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