From 1c5d2265a82f8d3fa0471a60ca98072b3c53c299 Mon Sep 17 00:00:00 2001 From: Michael Hennerich Date: Thu, 21 Jun 2007 11:34:16 +0800 Subject: Blackfin arch: add missing implementations SIC_IWR crosses several registers SIC_IWR crosses several registers - add missing implementations - make sure SIC_IWR is SET after boot Signed-off-by: Michael Hennerich Signed-off-by: Bryan Wu --- include/asm-blackfin/mach-bf561/cdefBF561.h | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) (limited to 'include/asm-blackfin/mach-bf561/cdefBF561.h') diff --git a/include/asm-blackfin/mach-bf561/cdefBF561.h b/include/asm-blackfin/mach-bf561/cdefBF561.h index b14f872e5703..6e8b8168a97a 100644 --- a/include/asm-blackfin/mach-bf561/cdefBF561.h +++ b/include/asm-blackfin/mach-bf561/cdefBF561.h @@ -57,12 +57,14 @@ /* Writing to VR_CTL initiates a PLL relock sequence. */ static __inline__ void bfin_write_VR_CTL(unsigned int val) { - unsigned long flags, iwr; + unsigned long flags, iwr0, iwr1; /* Enable the PLL Wakeup bit in SIC IWR */ - iwr = bfin_read32(SICA_IWR0); + iwr0 = bfin_read32(SICA_IWR0); + iwr1 = bfin_read32(SICA_IWR1); /* Only allow PPL Wakeup) */ bfin_write32(SICA_IWR0, IWR_ENABLE(0)); + bfin_write32(SICA_IWR1, 0); bfin_write16(VR_CTL, val); __builtin_bfin_ssync(); @@ -70,7 +72,9 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) local_irq_save(flags); asm("IDLE;"); local_irq_restore(flags); - bfin_write32(SICA_IWR0, iwr); + bfin_write32(SICA_IWR0, iwr0); + bfin_write32(SICA_IWR1, iwr1); + } #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val) -- cgit v1.2.3 From c04d66bbbdbbc7b5d55c42795f29e494190f8fb3 Mon Sep 17 00:00:00 2001 From: Bryan Wu Date: Thu, 12 Jul 2007 17:26:31 +0800 Subject: Blackfin arch: clean up some coding style issues Signed-off-by: Bryan Wu --- arch/blackfin/mach-common/ints-priority-dc.c | 4 ++-- arch/blackfin/mach-common/ints-priority-sc.c | 13 ++++++------- include/asm-blackfin/mach-bf548/cdefBF54x_base.h | 1 - include/asm-blackfin/mach-bf561/cdefBF561.h | 1 - include/asm-blackfin/mman.h | 2 -- 5 files changed, 8 insertions(+), 13 deletions(-) (limited to 'include/asm-blackfin/mach-bf561/cdefBF561.h') diff --git a/arch/blackfin/mach-common/ints-priority-dc.c b/arch/blackfin/mach-common/ints-priority-dc.c index 7977c2c40867..6b9fd03ce835 100644 --- a/arch/blackfin/mach-common/ints-priority-dc.c +++ b/arch/blackfin/mach-common/ints-priority-dc.c @@ -371,8 +371,8 @@ int __init init_arch_irq(void) bfin_write_SICA_IMASK1(SIC_UNMASK_ALL); SSYNC(); - bfin_write_SICA_IWR0(IWR_ENABLE_ALL); - bfin_write_SICA_IWR1(IWR_ENABLE_ALL); + bfin_write_SICA_IWR0(IWR_ENABLE_ALL); + bfin_write_SICA_IWR1(IWR_ENABLE_ALL); local_irq_disable(); diff --git a/arch/blackfin/mach-common/ints-priority-sc.c b/arch/blackfin/mach-common/ints-priority-sc.c index c3bb2fbd6428..28a878c3577a 100644 --- a/arch/blackfin/mach-common/ints-priority-sc.c +++ b/arch/blackfin/mach-common/ints-priority-sc.c @@ -147,8 +147,8 @@ static void bfin_internal_mask_irq(unsigned int irq) unsigned mask_bank, mask_bit; mask_bank = (irq - (IRQ_CORETMR + 1)) / 32; mask_bit = (irq - (IRQ_CORETMR + 1)) % 32; - bfin_write_SIC_IMASK( mask_bank, bfin_read_SIC_IMASK(mask_bank) & \ - ~(1 << mask_bit)); + bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) & + ~(1 << mask_bit)); #endif SSYNC(); } @@ -161,9 +161,9 @@ static void bfin_internal_unmask_irq(unsigned int irq) #else unsigned mask_bank, mask_bit; mask_bank = (irq - (IRQ_CORETMR + 1)) / 32; - mask_bit = (irq - (IRQ_CORETMR + 1))%32; - bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) | \ - ( 1 << mask_bit)); + mask_bit = (irq - (IRQ_CORETMR + 1)) % 32; + bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) | + (1 << mask_bit)); #endif SSYNC(); } @@ -728,7 +728,7 @@ int __init init_arch_irq(void) bfin_write_SIC_IMASK2(SIC_UNMASK_ALL); bfin_write_SIC_IWR0(IWR_ENABLE_ALL); bfin_write_SIC_IWR1(IWR_ENABLE_ALL); - bfin_write_SIC_IWR2(IWR_ENABLE_ALL); + bfin_write_SIC_IWR2(IWR_ENABLE_ALL); #else bfin_write_SIC_IMASK(SIC_UNMASK_ALL); bfin_write_SIC_IWR(IWR_ENABLE_ALL); @@ -878,7 +878,6 @@ void do_irq(int vec, struct pt_regs *fp) sic_status[0] = bfin_read_SIC_ISR(0) & bfin_read_SIC_IMASK(0); sic_status[1] = bfin_read_SIC_ISR(1) & bfin_read_SIC_IMASK(1); sic_status[2] = bfin_read_SIC_ISR(2) & bfin_read_SIC_IMASK(2); - for (;; ivg++) { if (ivg >= ivg_stop) { diff --git a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h index 87f2385ed971..98d35a929116 100644 --- a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h +++ b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h @@ -68,7 +68,6 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) bfin_write32(SIC_IWR0, iwr0); bfin_write32(SIC_IWR1, iwr1); bfin_write32(SIC_IWR2, iwr2); - } #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) diff --git a/include/asm-blackfin/mach-bf561/cdefBF561.h b/include/asm-blackfin/mach-bf561/cdefBF561.h index 6e8b8168a97a..1a8ec9e46922 100644 --- a/include/asm-blackfin/mach-bf561/cdefBF561.h +++ b/include/asm-blackfin/mach-bf561/cdefBF561.h @@ -74,7 +74,6 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) local_irq_restore(flags); bfin_write32(SICA_IWR0, iwr0); bfin_write32(SICA_IWR1, iwr1); - } #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val) diff --git a/include/asm-blackfin/mman.h b/include/asm-blackfin/mman.h index 4d504f908c0c..b58f5ad3f024 100644 --- a/include/asm-blackfin/mman.h +++ b/include/asm-blackfin/mman.h @@ -22,8 +22,6 @@ #define MAP_NORESERVE 0x4000 /* don't check for reservations */ #define MAP_POPULATE 0x8000 /* populate (prefault) pagetables */ #define MAP_NONBLOCK 0x10000 /* do not block on IO */ -#define MAP_UNINITIALIZE 0x4000000 /* For anonymous mmap, memory could - be uninitialized. */ #define MS_ASYNC 1 /* sync memory asynchronously */ #define MS_INVALIDATE 2 /* invalidate the caches */ -- cgit v1.2.3