From ea37ccea66e6bdd9f3571418b6461850088c114e Mon Sep 17 00:00:00 2001 From: Daniele Venzano Date: Tue, 11 Oct 2005 09:44:30 +0200 Subject: [PATCH] Add Wake on LAN support to sis900 (2) Sorry, but that day I had smoked somthing too heavy for me, the patch didn't apply. Here's a new one. The patch availble below adds support for Wake on LAN to the sis900 driver. Some register addresses were added to sis900.h and two new functions were implemented in sis900.c. WoL status is controlled by ethtool. Patch is against 2.6.13. Comments are welcome, but also consider for inclusion in the -mm series. Signed-off-by: Daniele Venzano -- Signed-off-by: Jeff Garzik --- drivers/net/sis900.h | 45 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) (limited to 'drivers/net/sis900.h') diff --git a/drivers/net/sis900.h b/drivers/net/sis900.h index de3c06735d15..4233ea55670f 100644 --- a/drivers/net/sis900.h +++ b/drivers/net/sis900.h @@ -33,6 +33,7 @@ enum sis900_registers { rxcfg=0x34, //Receive Configuration Register flctrl=0x38, //Flow Control Register rxlen=0x3c, //Receive Packet Length Register + cfgpmcsr=0x44, //Configuration Power Management Control/Status Register rfcr=0x48, //Receive Filter Control Register rfdr=0x4C, //Receive Filter Data Register pmctrl=0xB0, //Power Management Control Register @@ -140,6 +141,50 @@ enum sis96x_eeprom_command { EEREQ = 0x00000400, EEDONE = 0x00000200, EEGNT = 0x00000100 }; +/* PCI Registers */ +enum sis900_pci_registers { + CFGPMC = 0x40, + CFGPMCSR = 0x44 +}; + +/* Power management capabilities bits */ +enum sis900_cfgpmc_register_bits { + PMVER = 0x00070000, + DSI = 0x00100000, + PMESP = 0xf8000000 +}; + +enum sis900_pmesp_bits { + PME_D0 = 0x1, + PME_D1 = 0x2, + PME_D2 = 0x4, + PME_D3H = 0x8, + PME_D3C = 0x10 +}; + +/* Power management control/status bits */ +enum sis900_cfgpmcsr_register_bits { + PMESTS = 0x00004000, + PME_EN = 0x00000100, // Power management enable + PWR_STA = 0x00000003 // Current power state +}; + +/* Wake-on-LAN support. */ +enum sis900_power_management_control_register_bits { + LINKLOSS = 0x00000001, + LINKON = 0x00000002, + MAGICPKT = 0x00000400, + ALGORITHM = 0x00000800, + FRM1EN = 0x00100000, + FRM2EN = 0x00200000, + FRM3EN = 0x00400000, + FRM1ACS = 0x01000000, + FRM2ACS = 0x02000000, + FRM3ACS = 0x04000000, + WAKEALL = 0x40000000, + GATECLK = 0x80000000 +}; + /* Management Data I/O (mdio) frame */ #define MIIread 0x6000 #define MIIwrite 0x5002 -- cgit v1.2.1