From aca58a662067606e6020e1d42ced1b88cab65ca1 Mon Sep 17 00:00:00 2001 From: David Daney Date: Mon, 29 Jul 2013 14:29:10 -0700 Subject: gpio MIPS/OCTEON: Add a driver for OCTEON's on-chip GPIO pins. The SOCs in the OCTEON family have 16 (or in some cases 20) on-chip GPIO pins, this driver handles them all. Configuring the pins as interrupt sources is handled elsewhere (OCTEON's irq handling code). Signed-off-by: David Daney Reviewed-by: Linus Walleij Cc: linux-gpio@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/5633/ Signed-off-by: Ralf Baechle --- drivers/gpio/Kconfig | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'drivers/gpio/Kconfig') diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index b2450ba14138..b21b7a2d1c3d 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -193,6 +193,14 @@ config GPIO_MXS select GPIO_GENERIC select GENERIC_IRQ_CHIP +config GPIO_OCTEON + tristate "Cavium OCTEON GPIO" + depends on GPIOLIB && CAVIUM_OCTEON_SOC + default y + help + Say yes here to support the on-chip GPIO lines on the OCTEON + family of SOCs. + config GPIO_PL061 bool "PrimeCell PL061 GPIO support" depends on ARM && ARM_AMBA -- cgit v1.2.1