From b35d7c33419cb0d000d23d3a5ab524ab8d3d8bf9 Mon Sep 17 00:00:00 2001 From: Andrew Bresticker Date: Tue, 24 Feb 2015 19:56:04 -0800 Subject: CLK: Pistachio: Register core clocks Register the clocks generated by the core clock controller. This includes the 7 PLLs and clocks for the CPU, RPU co-processor, audio, WiFi, bluetooth, and several other peripherals. The MIPS and PERIPH_SYS clocks must remain enabled at all times. Signed-off-by: Damien Horsley Signed-off-by: Andrew Bresticker Cc: Mike Turquette Cc: Stephen Boyd Cc: devicetree@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: Ezequiel Garcia Cc: James Hartley Cc: James Hogan Acked-by: Stephen Boyd Patchwork: https://patchwork.linux-mips.org/patch/9317/ Signed-off-by: Ralf Baechle --- drivers/clk/pistachio/Makefile | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/clk/pistachio/Makefile') diff --git a/drivers/clk/pistachio/Makefile b/drivers/clk/pistachio/Makefile index a93490dbe3e1..f1e151fbef65 100644 --- a/drivers/clk/pistachio/Makefile +++ b/drivers/clk/pistachio/Makefile @@ -1,2 +1,3 @@ obj-y += clk.o obj-y += clk-pll.o +obj-y += clk-pistachio.o -- cgit v1.2.1