From 07afb8db7340f9b6051a26c5c28f2ce74148f6b5 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Wed, 21 Mar 2018 09:20:12 -0500 Subject: clk: socfpga: stratix10: add clock driver for Stratix10 platform Add a clock driver for the Stratix10 SoC. The driver is similar to the Cyclone5/Arria10 platforms, with the exception that this driver only uses one single clock binding. Signed-off-by: Dinh Nguyen Signed-off-by: Stephen Boyd --- drivers/clk/Makefile | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/clk/Makefile') diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 71ec41e6364f..80ab422438ee 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -88,6 +88,7 @@ obj-$(CONFIG_ARCH_SOCFPGA) += socfpga/ obj-$(CONFIG_PLAT_SPEAR) += spear/ obj-$(CONFIG_ARCH_SPRD) += sprd/ obj-$(CONFIG_ARCH_STI) += st/ +obj-$(CONFIG_ARCH_STRATIX10) += socfpga/ obj-$(CONFIG_ARCH_SUNXI) += sunxi/ obj-$(CONFIG_ARCH_SUNXI) += sunxi-ng/ obj-$(CONFIG_ARCH_TEGRA) += tegra/ -- cgit v1.2.1