From b93b2abce497873be97d765b848e0a955d29f200 Mon Sep 17 00:00:00 2001 From: David Daney Date: Fri, 1 Oct 2010 13:27:34 -0700 Subject: MIPS: Octeon: Rewrite DMA mapping functions. All Octeon chips can support more than 4GB of RAM. Also due to how Octeon PCI is setup, even some configurations with less than 4GB of RAM will have portions that are not accessible from 32-bit devices. Enable the swiotlb code to handle the cases where a device cannot directly do DMA. This is a complete rewrite of the Octeon DMA mapping code. Signed-off-by: David Daney Patchwork: http://patchwork.linux-mips.org/patch/1639/ Signed-off-by: Ralf Baechle --- arch/mips/cavium-octeon/Kconfig | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/mips/cavium-octeon/Kconfig') diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig index 47323ca452dc..475156b0c807 100644 --- a/arch/mips/cavium-octeon/Kconfig +++ b/arch/mips/cavium-octeon/Kconfig @@ -87,3 +87,15 @@ config ARCH_SPARSEMEM_ENABLE config CAVIUM_OCTEON_HELPER def_bool y depends on OCTEON_ETHERNET || PCI + +config IOMMU_HELPER + bool + +config NEED_SG_DMA_LENGTH + bool + +config SWIOTLB + def_bool y + depends on CPU_CAVIUM_OCTEON + select IOMMU_HELPER + select NEED_SG_DMA_LENGTH -- cgit v1.2.1